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SM320VC5510A-EP Datasheet, PDF (52/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor | |||
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Electrical Specifications
5.7 Memory Timing
5.7.1 Asynchronous Memory Timing
Table 5â7 and Table 5â8 assume testing over recommended operating conditions (see Figure 5â4 and
Figure 5â5). Note that the asynchronous memory interface is read-only when configured as 8-bit mode.
Asynchronous writes in 8-bit mode are not supported.
Table 5â7. Asynchronous Memory Cycles Timing Requirements
VC5510-200
NO.
UNIT
MIN MAX
A6 tsu(DV-COH)
Setup time, read data valid before CLKOUT highâ
6
ns
A7 th(COH-DV)
Hold time, read data valid after CLKOUT high
0
ns
A10 tsu(ARDY-COH)
Setup time, ARDY valid before CLKOUT high
7
ns
A11 th(COH-ARDY)
Hold time, ARDY valid after CLKOUT high
0
ns
â To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5â8. Asynchronous Memory Cycles Switching Characteristicsâ¡Â§
VC5510-200
NO.
PARAMETER
UNIT
MIN MAX
A1 td(COH-CEV)
Delay time, CLKOUT high to CEx transition
A2 td(COH-BEV)
Delay time, CLKOUT high to BEx valid
A3 td(COH-BEIV)
Delay time, CLKOUT high to BEx invalid
A4 td(COH-AV)
Delay time, CLKOUT high to address valid
A5 td(COH-AIV)
Delay time, CLKOUT high to address invalid
A8 td(COH-AOEV)
Delay time, CLKOUT high to AOE valid
A9 td(COH-AREV)
Delay time, CLKOUT high to ARE valid
A12 td(COH-DV)
Delay time, CLKOUT high to data valid (write)
A13 td(COH-DIV)
Delay time, CLKOUT high to data invalid (write)
A14 td(COH-AWEV)
Delay time, CLKOUT high to AWE valid
â¡ The minimum delay is also the minimum output hold after CLKOUT high.
§ All timings referenced to CLKOUT assume CLKOUT represents the internal CPU clock (divide-by-1 mode).
â2
4 ns
4 ns
â2
ns
4 ns
â2
ns
â2
4 ns
â2
4 ns
4 ns
â2
ns
â2
4 ns
44 SGUS045A
August 2003 â Revised November 2003
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