SM320VC5510A-EP Datasheet, PDF (17/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
RESET
RST_MODE
TYPE†
I
I
OTHER‡
DESCRIPTION
INTERRUPT AND RESET SIGNALS
C
Device reset. RESET causes the DSP to terminate execution and causes reinitialization of the
CPU and peripherals. The response of the DSP after reset is determined by the RST_MODE pin.
Device reset mode control. RST_MODE controls how a device reset is handled.
As of revision 2.1, the RST_MODE function will no longer be supported. RST_MODE will be
driven low internally. After reset, the CPU will branch to the reset vector and begin execution.
The external state of the RST_MODE pin will have no effect on device operation.
INT0
INT1
INT2
INT3
INT4
INT5
Maskable external interrupts. INT0−INT5 are prioritized and are maskable via the interrupt
I
C
enable registers (IER0 and IER1) and the Interrupt Mode bit (INTM in ST1_55). INT0−INT5 can
be polled and reset via the Interrupt Flag Registers (IFR0 and IFR1).
Nonmaskable external interrupt. NMI is an external interrupt that cannot be masked by the
NMI
I
C
interrupt enable registers (IER0 and IER1). When NMI is activated, the interrupt is always
performed.
JTAG EMULATION
TCK
IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty
I
A,C
cycle. The changes on the test access port (TAP) of input signals TDI and TMS are clocked into
the TAP controller, instruction register, or selected test data register on the rising edge of TCK.
Changes at the TAP output signal TDO occur on the falling edge of TCK.
TDI
I
A
IEEE Standard 1149.1 test data input. TDI is clocked into the selected register (instruction or
data) on the rising edge of TCK.
TDO
IEEE Standard 1149.1 test data output. The contents of the selected register (instruction or
O
−
data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except
when the scanning of data is in progress.
TMS
I
A
IEEE Standard 1149.1 test mode select. This serial control input is clocked into the TAP
controller on the rising edge of TCK.
IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system
control of the operations of the device. If TRST is not connected, or driven low, the device operates
TRST
I
B
in its functional mode, and the IEEE standard 1149.1 signals are ignored.
This pin has an on-chip pulldown circuit to provide control of the pin when it is not externally
connected. An external pullup resistor should not be connected to this pin.
† _{I = Input, O = Output, S = Supply, Z = High impedance}
‡ _{Other Pin Characteristics:}
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
August 2003 − Revised November 2003
SGUS045A
9