SM320VC5510A-EP Datasheet, PDF (35/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
Table 3−13. DMA Configuration Registers (Continued)
PORT ADDRESS
REGISTER NAME
DESCRIPTION
CHANNEL #4 REGISTERS
0x0C80
0x0C81
0x0C82
0x0C83
0x0C84
0x0C85
0x0C86
0x0C87
0x0C88
0x0C89
0x0C8A
DMA_CSDP4
DMA_CCR4
DMA_CICR4
DMA_CSR4
DMA_CSSA_L4
DMA_CSSA_U4
DMA_CDSA_L4
DMA_CDSA_U4
DMA_CEN4
DMA_CFN4
DMA_CFI4/
DMA_CSFI4†
DMA Channel 4 Source / Destination Parameters Register
DMA Channel 4 Control Register
DMA Channel 4 Interrupt Control Register
DMA Channel 4 Status Register
DMA Channel 4 Source Start Address Register (lower bits)
DMA Channel 4 Source Start Address Register (upper bits)
DMA Channel 4 Source Destination Address Register (lower bits)
DMA Channel 4 Source Destination Address Register (upper bits)
DMA Channel 4 Element Number Register
DMA Channel 4 Frame Number Register
DMA Channel 4 Frame Index Register/
DMA Channel 4 Source Frame Index Register†
0x0C8B
DMA_CEI4/
DMA_CSEI4‡
DMA Channel 4 Element Index Register/
DMA Channel 4 Source Element Index Register‡
0x0C8C
0x0C8D
0x0C8E
0x0C8F
DMA_CSAC4
DMA_CDAC4
DMA_CDEI4
DMA_CDFI4
DMA Channel 4 Source Address Counter
DMA Channel 4 Destination Address Counter
DMA Channel 4 Destination Element Index Register
DMA Channel 4 Destination Frame Index Register
CHANNEL #5 REGISTERS
0x0CA0
0x0CA1
0x0CA2
0x0CA3
0x0CA4
0x0CA5
0x0CA6
0x0CA7
0x0CA8
0x0CA9
0x0CAA
DMA_CSDP5
DMA_CCR5
DMA_CICR5
DMA_CSR5
DMA_CSSA_L5
DMA_CSSA_U5
DMA_CDSA_L5
DMA_CDSA_U5
DMA_CEN5
DMA_CFN5
DMA_CFI5/
DMA_CSFI5†
DMA Channel 5 Source / Destination Parameters Register
DMA Channel 5 Control Register
DMA Channel 5 Interrupt Control Register
DMA Channel 5 Status Register
DMA Channel 5 Source Start Address Register (lower bits)
DMA Channel 5 Source Start Address Register (upper bits)
DMA Channel 5 Source Destination Address Register (lower bits)
DMA Channel 5 Source Destination Address Register (upper bits)
DMA Channel 5 Element Number Register
DMA Channel 5 Frame Number Register
DMA Channel 5 Frame Index Register/
DMA Channel 5 Source Frame Index Register†
0x0CAB
DMA_CEI5/
DMA_CSEI5‡
DMA Channel 5 Element Index Register/
DMA Channel 5 Source Element Index Register‡
0x0CAC
DMA_CSAC5
DMA Channel 5 Source Address Counter
0x0CAD
DMA_CDAC5
DMA Channel 5 Destination Address Counter
0x0CAE
DMA_CDEI5
DMA Channel 5 Destination Element Index Register
0x0CAF
DMA_CDFI5
DMA Channel 5 Destination Frame Index Register
† _{On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and}
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ _{On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0}
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
August 2003 − Revised November 2003
SGUS045A
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