SM320VC5510A-EP Datasheet, PDF (33/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
Table 3−13. DMA Configuration Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x0E00
0x0E02
0x0E03
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
DMA_GCR
DMA_GSCR
DMA_GTCR
DMA_CSDP0
DMA_CCR0
DMA_CICR0
DMA_CSR0
DMA_CSSA_L0
DMA_CSSA_U0
DMA_CDSA_L0
DMA_CDSA_U0
DMA_CEN0
DMA_CFN0
DMA_CFI0/
DMA_CSFI0†
DMA_CEI0/
DMA_CSEI0‡
DMA_CSAC0
DMA_CDAC0
DMA_CDEI0
DMA_CDFI0
GLOBAL REGISTER
DMA Global Control Register
DMA Software Compatibility Register
DMA Timeout Control Register
CHANNEL #0 REGISTERS
DMA Channel 0 Source / Destination Parameters Register
DMA Channel 0 Control Register
DMA Channel 0 Interrupt Control Register
DMA Channel 0 Status Register
DMA Channel 0 Source Start Address Register (lower bits)
DMA Channel 0 Source Start Address Register (upper bits)
DMA Channel 0 Source Destination Address Register (lower bits)
DMA Channel 0 Source Destination Address Register (upper bits)
DMA Channel 0 Element Number Register
DMA Channel 0 Frame Number Register
DMA Channel 0 Frame Index Register/
DMA Channel 0 Source Frame Index Register†
DMA Channel 0 Element Index Register/
DMA Channel 0 Source Element Index Register‡
DMA Channel 0 Source Address Counter
DMA Channel 0 Destination Address Counter
DMA Channel 0 Destination Element Index Register
DMA Channel 0 Destination Frame Index Register
CHANNEL #1 REGISTERS
0x0C20
DMA_CSDP1
DMA Channel 1 Source / Destination Parameters Register
0x0C21
DMA_CCR1
DMA Channel 1 Control Register
0x0C22
DMA_CICR1
DMA Channel 1 Interrupt Control Register
0x0C23
DMA_CSR1
DMA Channel 1 Status Register
0x0C24
DMA_CSSA_L1
DMA Channel 1 Source Start Address Register (lower bits)
0x0C25
DMA_CSSA_U1
DMA Channel 1 Source Start Address Register (upper bits)
0x0C26
DMA_CDSA_L1
DMA Channel 1 Source Destination Address Register (lower bits)
0x0C27
DMA_CDSA_U1
DMA Channel 1 Source Destination Address Register (upper bits)
0x0C28
DMA_CEN1
DMA Channel 1 Element Number Register
0x0C29
DMA_CFN1
DMA Channel 1 Frame Number Register
0x0C2A
DMA_CFI1/
DMA_CSFI1†
DMA Channel 1 Frame Index Register/
DMA Channel 1 Source Frame Index Register†
0x0C2B
DMA_CEI1/
DMA_CSEI1‡
DMA Channel 1 Element Index Register/
DMA Channel 1 Source Element Index Register‡
0x0C2C
DMA_CSAC1
DMA Channel 1 Source Address Counter
0x0C2D
DMA_CDAC1
DMA Channel 1 Destination Address Counter
0x0C2E
DMA_CDEI1
DMA Channel 1 Destination Element Index Register
0x0C2F
DMA_CDFI1
DMA Channel 1 Destination Frame Index Register
† _{On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and}
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ _{On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0}
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
August 2003 − Revised November 2003
SGUS045A
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