SM320VC5510A-EP Datasheet, PDF (71/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)^†‡
VC5510-200
NO.
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
4
3 − 6P
ns
1
1 +6P
ns
M41 tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
10
ns
M42 tc(CKX)
Cycle time, CLKX
2P
16P
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)^†‡
NO.
M34 td(CKXL-FXL)
M35 td(FXL-CKXH)
M36 td(CKXL-DXV)
M37 tdis(CKXL-DXHZ)
PARAMETER
Delay time, FSX low to CLKX low¶
Delay time, FSX low to CLKX high#
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX low
VC5510-200
MASTER§
SLAVE
MIN MAX
MIN
MAX
C−1 C+3
T−2 T+2
−2
4 3P + 2 5P + 8
−2
0 3P + 8 3P + 21
UNIT
ns
ns
ns
ns
M38 td(FXL-DXV)
Delay time, FSX low to DX valid
D − 2 D +10 3P − 3 3P + 21 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
FSX
DX
DR
LSB
M41
MSB
M42
M34
M35
M37
Bit 0
Bit 0
M38
M39
Bit(n-1)
Bit(n-1)
M36
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
August 2003 − Revised November 2003
SGUS045A
63