SM320VC5510A-EP Datasheet, PDF (18/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE† OTHER‡
DESCRIPTION
JTAG EMULATION (CONTINUED)
EMU0
I/O/Z
Emulation pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF
A
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system
and is defined as input/output by way of the IEEE standard 1449.1 scan system.
EMU1/OFF
I/O/Z
Emulation pin 1 / disable all outputs. When TRST is driven high, EMU1/OFF is used as an
interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard
1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF
signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is
A
used exclusively for testing and emulation purposes (not for multiprocessing applications).
Therefore, for the OFF feature, the following apply:
TRST = low
EMU0 = high
EMU1/OFF = low
RSVD[1:9]
I/O
Reserved. Reserved for future emulation purposes. These pins should be left unconnected.
CLOCK SIGNALS
CLKIN
I
C
Clock input
CLKOUT
O/Z
F
Clock output. CLKOUT can represent the internal CPU clock or can be divided down to generate
a slower clock by programming the CLKDIV field in the system register (SYSR).
CLKMD
I
Clock mode select. CLKMD selects the mode of the clock generator after reset. When CLKMD
C
is low after reset, the clock generator will run at the same frequency as CLKIN. If CLKMD is high
after reset, the clock generator will run at one-half of the frequency of CLKIN. The clock generator
can later be reprogrammed in software.
TIMERS
TIN/TOUT0
TIN/TOUT1
I/O/Z
Timer 0 input/output. When configured as an output, TIN/TOUT0 generates a pulse or toggles
F,H
when on-chip Timer 0 counts down to zero. When configured as an input, TIN/TOUT0 is used
as a clock reference for Timer 0. The operation of this pin is configured in the timer control register
(TCR0).
Timer 1 input/output. When configured as an output, TIN/TOUT1 generates a pulse or toggles
F,H
when on-chip Timer 1 counts down to zero. When configured as an input, TIN/TOUT1 is used
as a clock reference for Timer 1. The operation of this pin is configured in the timer control register
(TCR1).
GENERAL-PURPOSE I/O SIGNALS
IO7
IO6
IO5
IO4
IO3/BOOTM2
IO2/BOOTM1
IO1/BOOTM0
IO0
I/O/Z
F,G,H
General-purpose configurable inputs/outputs. IO[7:0] can be individually configured as inputs
or outputs via the GPIO direction register (IODIR). Data can be read from inputs or data written
to outputs via the GPIO Data Register (IODATA). In addition, the bootloader uses IO4 as an output
during the boot process. For detailed information on the operation of the bootloader, see the Using
the TMS320VC5510 Bootloader application report (literature number SPRA763).
Boot Mode Selection signals. BOOTM[2:0] are sampled following reset to configure the boot
mode for the DSP. These signals are shared with IO[3:1]. After boot is complete, these signals
can be used as general-purpose inputs/outputs.
BOOTM3
I
Boot Mode Selection signal. BOOTM3 is sampled during the operation of the on-chip
A
bootloader in conjunction with BOOTM[2:0] to configure the boot mode. BOOTM3 is not present
on TMX320VC5510 revision 1.x.
XF
O/Z
F,H
External flag output
† _{I = Input, O = Output, S = Supply, Z = High impedance}
‡ _{Other Pin Characteristics:}
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
10 SGUS045A
August 2003 − Revised November 2003