SM320VC5510A-EP Datasheet, PDF (70/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.14.3 McBSP as SPI Master or Slave Timing
Table 5−27 to Table 5−34 assume testing over recommended operating conditions (see Figure 5−24 through
Figure 5−27).
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)^†‡
VC5510-200
NO.
MASTER
SLAVE
UNIT
MIN MAX
MIN
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
4
3 − 6P
ns
1
1 + 6P
ns
M32 tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
10
ns
M33 tc(CKX)
Cycle time, CLKX
2P
16P
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)^†‡
NO.
M24 td(CKXL-FXL)
M25 td(FXL-CKXH)
M26 td(CKXH-DXV)
M27 tdis(CKXL-DXHZ)
PARAMETER
Delay time, FSX low to CLKX low¶
Delay time, FSX low to CLKX high#
Delay time, CLKX high to DX valid
Disable time, DX high impedance following
last data bit from CLKX low
VC5510-200
MASTER§
SLAVE
MIN
MAX
MIN
MAX
T−1
T+3
C−2 C+2
−2
4 3P + 2 5P+ 8
UNIT
ns
ns
ns
C−2
C
ns
M28 tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
3P + 8 3P + 20 ns
M29 td(FXL-DXV)
Delay time, FSX low to DX valid
3P − 3 3P + 20 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
LSB
M32
MSB
M33
FSX
DX
Bit 0
DR
Bit 0
M24
M28
M27
M25
M29
Bit(n-1)
M30
Bit(n-1)
M26
(n-2)
M31
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
62 SGUS045A
August 2003 − Revised November 2003