SM320VC5510A-EP Datasheet, PDF (72/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)^†‡
VC5510-200
NO.
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
4
3 − 6P
ns
1
1 + 6P
ns
M51 tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
10
ns
M52 tc(CKX)
Cycle time, CLKX
2P
16P
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)^†‡
NO.
M43 td(CKXH-FXL)
M44 td(FXL-CKXL)
M45 td(CKXL-DXV)
M46 tdis(CKXH-DXHZ)
PARAMETER
Delay time, FSX low to CLKX high¶
Delay time, FSX low to CLKX low#
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX high
VC5510-200
MASTER§
SLAVE
MIN MAX
MIN
MAX
T−1 T+3
D−2 D+2
−2
4 3P + 2 5P + 8
D−2
D
UNIT
ns
ns
ns
ns
M47 tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
3P + 8 3P + 20 ns
M48 td(FXL-DXV)
Delay time, FSX low to DX valid
3P − 3 3P + 20 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
LSB
M51
MSB
M52
FSX
DX
Bit 0
DR
Bit 0
M43
M47
M46
M48
M49
M44
Bit(n-1)
Bit(n-1)
M45
(n-2)
M50
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
64 SGUS045A
August 2003 − Revised November 2003