SM320VC5510A-EP Datasheet, PDF (79/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

HCS
E11
HAS
HDS
E19
HR/W
E20
E13
Read
E12
E15
E14
Electrical Specifications
Write
E11
E12
E16
E15
E19
E20
E13
E14
HCNTL[1:0]
Valid (10 or 00)
Valid (10 or 00)
HD[15:0]
(read)
HD[15:0]
(write)
E5
E4
E6
Read Data
E17
E18
Write Data
HRDY
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. During auto-increment mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−32. EHPI Multiplexed Register Access Read/Write Timings
August 2003 − Revised November 2003
SGUS045A
71