SM320VC5510A-EP Datasheet, PDF (22/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
3.1.3 On-Chip ROM
The ROM is located at the byte address range FF8000h−FFFFFFh when MP/MC = 0 at reset. The ROM is
composed of a single block of 32K bytes. When MP/MC = 1 at reset, the on-chip ROM is disabled and not
present in the memory map, and byte address range FF8000h−FFFFFFh is directed to external memory
space. MP/MC is a bit located in the ST3 status register, and its status is determined by the logic level on the
BOOTM[2:0] pins when sampled at reset. If BOOTM[2:0] are all logic 0 at reset, the MP/MC bit is set to 1 and
the on-chip ROM is disabled; otherwise, the MP/MC bit is cleared to 0 and the on-chip ROM is enabled. These
pins are not sampled again until the next hardware reset. The software reset instruction does not affect the
MP/MC bit. Software can also be used to set or clear the MP/MC bit. ROM can be accessed by the program,
data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require
two cycles per 16-bit word.
The standard on-chip ROM contains a bootloader which provides a variety of methods to load application code
automatically after power up or a hardware reset. For more information, see Section 3.1.5 of this document.
The vector table associated with the bootloader is also contained in the ROM.
A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format.
The remaining components are used during factory testing purposes.
Table 3−3. Standard On-Chip ROM Contents
BYTE ADDRESS RANGE
FF8000h − FF8FFFh
FF9000h − FFF9FFh
FFFA00h − FFFBFFh
FFFC00h − FFFEFFh
FFFF00h − FFFFFBh
FFFFFCh − FFFFFFh
DESCRIPTION
Bootloader
Reserved
Sine look-up table
Factory Test Code
Vector Table
ID Code
3.1.4 Instruction Cache
The 24K-byte instruction cache provides three configurations:
• One 2-way cache block only
• One 2-way cache block plus one RAMSET block
• One 2-way cache block plus two RAMSET blocks
The 2-way cache uses 2-way set associative mapping and holds up to 16K bytes. It is organized as 512 sets
of two cache lines per set. Each cache line contains 16 bytes. Each tag has two corresponding cache lines,
providing two opportunities for a hit on a given tag. The 2-way cache is updated based on a least-recently-used
algorithm.
Each RAMSET block provides a 4K-byte bank of memory to hold a continuous image of code. Each RAMSET
is composed of 256 lines with 16 bytes per line. Each RAMSET uses a single tag to define a continuous
memory image in the RAMSET. The tag defines the start address of the RAMSET. Once the TAG is loaded,
the RAMSET is filled. The RAMSET contents remain constant until the tag is changed. The RAMSETs provide
an efficient method to cache frequently used functions.
Control bits in CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache.
For more information on the instruction cache, see the TMS320C5510 DSP Instruction Cache Reference
Guide (literature number SPRU576).
14 SGUS045A
August 2003 − Revised November 2003