SM320VC5510A-EP Datasheet, PDF (62/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.9 Reset Timings
Table 5−15 and Table 5−16 assume testing over recommended operating conditions (see Figure 5−15).
Table 5−15. Reset Timing Requirements^†
NO.
R1 tw(RSL)
Pulse width, reset low
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
VC5510-200
MIN MAX
2P + 5
UNIT
ns
Table 5−16. Reset Switching Characteristics^†
NO.
PARAMETER
VC5510-200
MIN
MAX
R3 td(RSL-EMIFHZ)
R4 td(RSL-EMIFV)
R5 td(RSL-LOWIV)
R6 td(RSL-LOWV)
Delay time, reset low to EMIF group high impedance‡
Delay time, reset low to EMIF group valid‡
Delay time, reset low to low group invalid§
Delay time, reset low to low group valid§
19
38P + 19
17
38P + 17
R7 td(RSL-HIGHIV)
R8 td(RSL-HIGHV)
Delay time, reset low to high group invalid§
Delay time, reset low to high group valid§
9
38P + 9
R9 td(RSL-ZHZ)
R10 td(RSL-ZV)
Delay time, reset low to Z group high impedance¶
Delay time, reset low to Z group valid¶
18
39P + 18
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{EMIF group: CE[0:3]}, _{BE[0:3], CLKMEM, ARE, AOE, AWE, SSADS, SSOE, SSWE, SDRAS, SDCAS, SDWE, and SDA10}
§ _{High group: HINT}
Low group: HOLDA
¶ _{Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
R1
RESET
R3
R4
EMIF Group^†
R5
R6
Low Group^‡
R7
R8
High Group^‡
R9
R10
Z Group^§
† _{EMIF group: CE[0:3]}, _{BE[0:3], CLKMEM, ARE, AOE, AWE, SSADS, SSOE, SSWE, SDRAS, SDCAS, SDWE, and SDA10}
‡ _{High group: HINT}
Low group: HOLDA
§ _{Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]}
Figure 5−15. Reset Timing
54 SGUS045A
August 2003 − Revised November 2003