SM320VC5510A-EP Datasheet, PDF (77/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

HCS
E11
E12
HAS
E15
E16
HDS
E19
E20
E13
E14
HR/W
Electrical Specifications
HCNTL[1:0]
Valid (01)
Valid (01)
HD[15:0]
(read)
HRDY
E2
E1
E6
Read Data
E7
E8
E2
E1
E6
Read Data
E7
E8
HPIA contents
n
n+1
n+2
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−30. EHPI Multiplexed Memory (HPID) Access Read Timings With Autoincrement
August 2003 − Revised November 2003
SGUS045A
69