LMH1982SQ-NOPB Datasheet, PDF (9/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Supported Standards and Timing Formats
Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used
to configure the LMH1982 for the input reference and output timing. For the related programming instructions,
see sections INPUT REFERENCE and OUTPUT CLOCKS AND TOF.
Format
NTSC, 525i
PAL, 625i
525p
625p
720p/60
720p/59.94
720p/50
720p/30
720p/29.97
720p/25
720p/24
720p/23.98
1080p/60
1080p/59.94
1080p/50
1080p/30
1080p/29.97
1080p/25
1080p/24
1080p/23.98
Table 1. Input Reference and Output Timing Parameters ⁽¹⁾⁽²⁾
INPUT TIMING PARAMETERS ⁽¹⁾
OUTPUT TIMING PARAMETERS ⁽²⁾
PLL 1
Reference
Divider¹⁽³⁾
PLL 1
Feedback
Divider
PLL 1 Phase
Comparison
Frequency
(kHz)
Total Lines
per Frame
Counter
Clock
Frequency
(MHz)
Total Clocks
per Line
Counter
Total Lines
per Frame
Counter
Frame Rate
(Hz)
1
1716
15.7343
525
27.0
1716
525
29.97
1
1728
15.625
625
27.0
1728
625
25
1
[5]
858
[4290]
31.4685
[6.2937]
525
[105]
27.0
858
525
59.94
1
864
31.25
[5]
[4320]
[6.25]
625
[125]
27.0
864
625
50
1
600
45.0
[5]
[3000]
[9.0]
750
[150]
74.25
(27.0)
1650
(600)
750
(750)
60
5
3003
8991.0090
750
74.176
(27.0)
1650
(3003)
750
(150)
59.94
1
720
37.5
[5]
[3600]
[7.5]
750
[150]
74.25
(27.0)
1980
(720)
750
(750)
50
1
1200
22.5
[5]
[6000]
[4.5]
750
[150]
74.25
(27.0)
3300
(1200)
750
(150)
30
5
6006
4.4955
750
74.176
(27.0)
3300
(6006)
750
(150)
29.97
1
1440
18.75
[5]
[7200]
[3.75]
750
[150]
74.25
(27.0)
3960
(1440)
750
(750)
25
1
1500
18.0
[5]
[7500]
[3.6]
750
[150]
74.25
(27.0)
4125
(1500)
750
(750)
24
2
3003
8991.0090
750
74.176
(27.0)
4125
(3003)
750
(375)
23.98
1
400
67.5
[5]
[2000]
[13.5]
1125
[225]
148.5
(27.0)
2200
(400)
1125
(1125)
60
5
2002
13.4865
1125
148.35
(27.0)
2200
(2002)
1125
(225)
59.94
1
[5]
480
[2400]
56.25
[11.25]
1125
[225]
148.5
(27.0)
2640
(480)
1125
(1125)
50
1
800
33.75
[5]
[4000]
[6.75]
1125
[225]
74.25
(27.0)
2200
(800)
1125
(1125)
30
5
4004
6.7433
1125
74.176
(27)
2200
(4004)
1125
(225)
29.97
1
[5]
960
[4800]
28.125
[5.625]
1125
[225]
74.25
(27.0)
2640
(960)
1125
(1125)
25
1
1000
27.0
[5]
[5000]
[5.4]
1125
[225]
74.25
(27.0)
2750
(1000)
1125
(1125)
24
1
[5]
1001
[5005]
26.9730
[5.3946]
1125
[225]
74.176
(27.0)
2750
(1001)
1125
(1125)
23.98
(1) For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in
brackets “[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The
corresponding counter values for REF_LPFM needs to be programmed for proper reference frame and output timing generation. See
section Reference Frame Timing.
(2) For any output HD format, an alternative set of counter values for total clocks per line (TOF_PPL) and total lines per frame (TOF_LPFM)
is shown in parenthesis “( )”. This alternative set of values can be programmed to generate any HD format TOF pulse using the 27
MHz SD_CLK instead of using the native 74.xx or 148.xx MHz HD_CLK. See section HD Format TOF Generation using a 27 MHz TOF
Clock.
(3) The PLL 1 reference divider value is not the same as the programming value for REF_DIV_SEL. See Table 3.
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