LMH1982SQ-NOPB Datasheet, PDF (25/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
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The -3 dB loop bandwidth, BW, can be approximated by:
BW = I_CP1 * R_S * K_VCO / FB_DIV
where
SNLS289C – APRIL 2008 – REVISED MARCH 2013
(9)
I_CP1 =
R_S =
K_VCO =
FB_DIV =
Nominal VCXO PLL charge pump current (in amps)
programmed by setting ICP1 (register 13h).
For example:
I_CP1 = 250 µA: ICP1 = 08h (default value)
I_CP1 = 0 µA: ICP1 = 00h (min)
I_CP1 = 62.5 µA; ICP1 = 02h (practical min)
I_CP1 = 968.75 µA; ICP1 = 1Fh (max)
I_CP1 step size = 31.25 µA
Nominal value of series resistor (in ohms)
Nominal 27 MHz VCXO gain (in Hz/V)
K_VCO = Pull_range * 27 MHz/Vin_range
For the recommended VCXO (Mftr: CTS, P/N: 357LB3C027M0000): K_VCO = 100 ppm * 27 MHz/(3.0V- 0.3V) = 1000 Hz/V
Feedback Divider value
For example:
FB_DIV =1716 for NTSC timing
Note that this BW approximation does not take into account the effects of the damping factor or the second pole
introduced by Cp.
At frequencies far above the −3 dB loop bandwidth, the closed-loop frequency response of PLL 1 will roll off at
about −40 dB/decade, which is useful attenuating input jitter at frequencies above the loop bandwidth. Near the
−3 dB corner frequency, the roll-off characteristic will depend on other factors, such as damping factor and filter
order.
To prevent output jitter due to the modulation of the VCXO by the PLL’s phase comparison frequency:
BW ≤ (27 MHz / FB_DIV) / 20
PLL 1's damping factor, DF, can be approximated by:
DF = (R_S / 2) * sqrt (I_CP1 * C_S * K_VCO / FB_DIV)
where
• C_S = Nominal value of the series capacitor (in farads)
(10)
A typical design target for DF is between 0.707 to 1, which can often yield a good trade-off between reference
spur attenuation and lock time. DF is related to the phase margin, which is a measure of the PLL stability.
A secondary parallel capacitor, C_P, is needed to filter the reference spurs introduced by the PLL which may
modulate the VCXO input voltage and also cause output jitter. The following relationship should be used to
determine C_P:
C_P = C_S / 20
(11)
The PLL loop gain, K, can be calculated as:
K = I_CP1 * K_VCO / FB_DIV
(12)
Therefore, the BW and DF can be expressed in terms of K:
BW = R_S * K
DF = (R_S/2) * sqrt (C_S * K)
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