LMH1982SQ-NOPB Datasheet, PDF (8/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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Typical Performance Characteristics
Test conditions: V_DD = 3.3V, D_VDD = 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are
from the LMH1981 sync separator, which receives an analog video reference signal from a Tektronix TG700 AVG7/AWVG7
(SD/HD) video signal generator. See Note section below for register settings (in decimal):
NTSC TOF Pulse
PAL TOF Pulse
NTSC
500 mV/DIV
PAL
500 mV/DIV
H sync
2.0V/DIV
V sync
2.0V/DIV
TOF
2.0V/DIV
1080i50
500 mV/DIV
TOF_OFFSET = 262
100 Ps/DIV
Figure 2.
1080i/50 TOF Pulse
H sync
2.0V/DIV
V sync
2.0V/DIV
TOF
2.0V/DIV
TOF_OFFSET = 562
40.0 Ps/DIV
Figure .
525i TOF Output Delay Using 27 MHz TOF Clock
SD_CLK
27 MHz
500 mV/DIV
H sync
2.0V/DIV
V sync
2.0V/DIV
TOF
2.0V/DIV
TOF_OFFSET = 312
100 Ps/DIV
Figure 3.
1080p/24 TOF Pulse
1080p24
500 mV/DIV
H sync
2.0V/DIV
V sync
2.0V/DIV
TOF
2.0V/DIV
TOF_OFFSET = 1124
40.0 Ps/DIV
Figure 4.
1080i/50 TOF Output Delay Using 74.25 MHz TOF Clock
HD_CLK
74.25 MHz
500 mV/DIV
H sync
2.0V/DIV
H sync
2.0V/DIV
TOF ^{tOD = 2 ns}
2.0V/DIV
10.0 ns/DIV
Figure 5.
TOF ^tOD ^{= 3.5 ns}
2.0V/DIV
10.0 ns/DIV
Figure 6.
(1) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525,
REF_LPFM = 525, TOF_OFFSET = 262; all other register settings are default
(2) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1728, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1728, TOF_LPFM = 625,
REF_LPFM = 625, TOF_OFFSET = 312; all other register settings are default
(3) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 960, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 960,
TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 562; all other register settings are default
(4) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1000, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1000,
TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 1124; all other register settings are default
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