LMH1982SQ-NOPB Datasheet, PDF (4/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
www.ti.com
Pin No.
–
1
2, 10, 18, 22, 26, 30
3, 21, 27, 28, 32
4
5
6
7
8
9
11
12
13
14
15
16
17
19, 20
23, 24
25
29
31
Pin Name
DAP
VC_FREERUN
GND
V_DD
HREF_A
VREF_A
REF_SEL
HREF_B
VREF_B
DV_DD
SDA
SCL
I²C_ENABLE
GENLOCK
RESET
NO_REF
NO_LOCK
HD_CLK, HD_CLK
SD_CLK, SD_CLK
TOF
VCXO
LPF
Pin Descriptions⁽¹⁾
I/O
Signal Level
–
Supply
I
Analog
–
Supply
–
Supply
I
LVCMOS
I
LVCMOS
I
LVCMOS
I
LVCMOS
I
LVCMOS
–
Supply
I/O
I²C
I
I²C
I
LVCMOS
I
LVCMOS
I
LVCMOS
O
LVCMOS
O
LVCMOS
O
LVDS
O
LVDS
O
LVCMOS
I
LVCMOS
O
Analog
Pin Description
Die Attach Pad (Connect to GND)
Free Run Control Voltage Input
Ground
3.3V Supply ¹
H sync Input, Reference A
V sync Input, Reference A
Reference Select ^{2, 3}
H sync Input, Reference B
V sync Input, Reference B
2.5V Supply ⁴
I²C Data ⁵
I²C Clock ⁵
I²C Enable
Mode Select ⁶
Device Reset
Reference Status Flag
Lock Status Flag
HD Clock Output
SD Clock Output
Top of Frame Pulse
VCXO Clock Input
VCXO PLL Loop Filter
(1) Notes
1. Refer to section Power Supply Sequencing.
2. To control reference selection via the REF_SEL pin instead of the I²C interface (default), program I²C_RSEL = 0 (register 00h).
3. To override reference control via pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1
(register 02h); accordingly, the TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled via I²C.
4. Must be ≤ V_DD +0.3V. Refer to section Power Supply Sequencing.
5. SDA and SCL pins each require a 4.7 kΩ (typ) pull-up resistor to the V_DD supply.
6. To control mode selection via the GENLOCK pin instead of the I²C interface (default), program I²C_GNLK = 0 (register 00h).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings ⁽¹⁾⁽²⁾
ESD Tolerance ⁽³⁾
Supply Voltage, V_DD
Supply Voltage, DV_DD
Input Voltage Range (any input)
Storage Temperature Range
Lead Temperature (Soldering 10 sec.)
Junction Temperature, T_JMAX
Thermal Resistance (θ_JA)
Human Body Model
Machine Model
2000V
200V
3.6V
2.75V
DV_DD ≤ V_DD +0.3V
−0.3V to V_DD +0.3V
−65°C to +150°C
300°C
150°C
33°C/W
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
4
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