LMH1982SQ-NOPB Datasheet, PDF (14/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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Genlock Mode State Diagram
Figure 7 shows the Genlock mode state diagram for different input reference and PLL lock conditions. It also
includes Free Run and Holdover states for the loss of reference operation, specified by the HOLDOVER bit
(register 00h). Each state indicates the NO_REF and NO_LOCK status flag output conditions.
Reference &
lock lost
PLL LOCKED
NO_REF = 0
NO_LOCK = 0
Reference &
lock lost
FREE RUN
NO_REF = 1
NO_LOCK = 1
Reg. 00h[3] = 0
Locked
Lock lost
HOLDOVER
NO_REF = 1
NO_LOCK = 1
Reg. 00h[3] = 1
Reference
valid & no lock
PLL LOCKING
NO_REF = 0
NO_LOCK = 1
Reference
valid & no lock
Figure 7. Genlock Mode State Diagram
Loss of Reference (LOR)
By configuring the HOLDOVER bit, the LMH1982 can default to either Free Run or Holdover operation when a
loss of reference (LOR) occurs in Genlock mode.
If HOLDOVER = 0 when a LOR occurs, the LMH1982 will default to Free run operation (section Free Run during
LOR) until a reference is reapplied.
If HOLDOVER = 1 when a LOR occurs, the LMH1982 will default to Holdover operation (section Holdover during
LOR) until a reference is reapplied.
When the input reference is reapplied, the LMH1982 will immediately attempt to phase lock the output clocks to
the reference.
Free Run during LOR
Free Run mode (GNLK = 0) differs from Free Run operation due to LOR in Genlock mode (GNLK = 1) in the
following way:
• In Free Run mode, the outputs will free run regardless of the presence or loss of reference.
• In Genlock mode, the outputs will free run only during LOR; once a reference is present, free run operation
will cease as the PLLs will immediately attempt to phase lock the output clocks to the reference.
Holdover during LOR
In Holdover operation, the LPF output is put into high impedance mode, which allows the loop filter to temporarily
hold the residual charge stored across it (i.e. the control voltage) immediately after LOR is indicated by the
NO_REF status flag. Holdover operation can help to temporarily sustain the output clock accuracy upon LOR.
The duration that the residual control voltage level can be sustained within a tolerable level depends primarily on
the charge leakage on the loop filter. A typical VCXO has an input impedance of several tens of kΩ, which will be
the dominant leakage path seen by the loop filter. As the leakage current discharges the residual control voltage
to GND, the output frequencies of the VCXO and LMH1982 will drift accordingly. If a longer time constant is
required, a precision op amp with low input bias current and rail-to-rail input and output (e.g. LMP7701) can be
used to buffer the control voltage. The buffer will isolate the relatively low input impedance of the VCXO and
reduce the charge leakage on the loop filter during Holdover.
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