LMH1982SQ-NOPB Datasheet, PDF (13/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Evaluating the LMH1982
For information about SDI jitter performance using the LMH1982 with the LMH1981 sync separator, please refer
to the following application notes:
• AN-1893: Demonstrating SMPTE-compliant SDI Output Jitter using the LMH1982 and Virtex-5 GTP
Transmitter (SNLA110)
• AN-1841: LMH1982 Evaluation Board User Guide (SNVA343)
The LMH1982SQEEVAL Evaluation Board can be ordered from Texas Instrument's website.
MODES OF OPERATION
The mode of operation describes the operation of PLL 1, which can operate in either Free Run mode or Genlock
mode depending on the GNLK bit setting. If desired, the GENLOCK input pin can be instead used to control the
mode of operation by initially setting I²C_GNLK = 0 (register 00h).
Free Run Mode
The LMH1982 will enter Free Run mode when GNLK is set to 0. In Free Run mode, the VCXO will be free-
running and independent of the input reference, and the output clocks will maintain phase lock to the VCXO
clock reference. Therefore, the output clocks will have the same accuracy as the VCXO clock reference.
The LMH1982 provides the designer with the option to define the VCXO's free run control voltage by external
biasing of the VC_FREERUN input (pin 1). The analog bias voltage applied to the VC_FREERUN input will be
connected to the LPF output (pin 31) though an internal switch (non-buffered, low impedance), as shown in the
Functional Block Diagram. The resultant voltage at the LPF output will drive the control input of the VCXO to set
its free run output frequency. Thus, the pull range of the VCXO imparts the same pull range on the free run
output clocks.
If VC_FREERUN is left floating, the VCXO control voltage will be pulled to GND potential as the residual charge
stored across the loop filter will discharge through any existing leakage path.
Genlock Mode
The LMH1982 will enter Genlock mode when GNLK is set to 1. In Genlock mode, PLL 1 can be phase locked to
the reference H sync input of the selected port; once the VCXO clock reference is locked and stable, the output
clocks and TOF pulse can be aligned and phase locked to the reference. The LMH1982 supports cross-locking,
which allows the outputs to be frame-locked to a reference format that is different from the output format.
To genlock the outputs, the following programming sequence is suggested:
1. Program the output clock frequency for the desired output format. Refer to section Programming The Output
Clock Frequencies.
2. Program the output TOF timing for the desired output format. Refer to section Programming The Output
Format Timing. It is required to complete this step for proper output clock initialization (alignment) even if the
TOF pulse is not required.
3. Program the PLL 1 divider registers for the input reference format. Refer to section Programming the PLL 1
Dividers.
4. Program GNLK = 1 to enable Genlock mode. See below.
5. Program the output initialization to the desired reference frame. Refer to section Programming The Output
Initialization Sequence.
NOTE
When Genlock mode is enabled, the LMH1982 will attempt to phase lock the PLLs to the
input reference regardless of input timing stability. Timing errors or instability on the inputs
will cause the PLLs and outputs to also have instability. If output stability is a consideration
during periods of input uncertainty, it is suggested to gate off the input signals from the
LMH1982 until they are completely stable. Input signal gating can be achieved externally
using a discrete or FPGA logic buffer with Hi-Z (tri-state) output and a pull-up or pull-down
resistor, depending on the input pulse signal polarity.
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