LMH1982SQ-NOPB Datasheet, PDF (34/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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This bit should be programmed to select the output TOF clock reference according to the desired output format.
The selected TOF clock frequency is used in specifying the output frame rate. Any output format, including HD,
can use 27 MHz as the TOF clock to generate its TOF pulse by programming the output counter values
corresponding to the 27 MHz SD clock as shown in Table 1. See sections Output TOF Clock and Output Frame
Timing.
TOF_CLK = 0: Selects the SD_CLK output as the output clock reference, where the SD frequency is set by
SD_FREQ.
TOF_CLK = 1: Selects the HD_CLK output as the output clock reference.
Bit 7-6: These non-programmable bits contain zeros.
Register 0Dh
Bits 7-0: LSBs of Total Lines per Frame for the Output Format (TOF_LPFM)
This register contains the 8 LSBs of TOF_LPFM. TOF_LPFM should be programmed with the total lines per
frame for the desired output format. TOF_LPFM is used in specifying the output frame rate. This should be
specified prior to programming the output initialization sequence. See section Output Frame Timing.
Register 0Eh
Bits 3-0: MSBs of Total Lines per Frame for the Output Format (TOF_LPFM)
This register contains the 4 MSBs of TOF_LPFM. See the description for register 0Dh.
Bit 7-5: These non-programmable bits contain zeros.
Register 0Fh
Bits 7-0: LSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM)
This register contains the 8 LSBs of REF_LPFM. REF_LPFM should be programmed with the total lines per
frame for the input reference format. REF_LPFM is used in specifying the reference frame rate. This should be
specified prior to programming the output initialization sequence (section Reference Frame Timing).
Register 10h
Bits 3-0: MSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM)
This register contains the 4 MSBs of REF_LPFM. See the description for register 0Fh.
Bit 7-4: These non-programmable bits contain zeros.
Register 11h
Bits 7-0: LSBs of Output Frame Offset (TOF_OFFSET)
This register contains the 8 LSBs of TOF_OFFSET. TOF_OFFSET should be programmed with the desired line
offset to delay or advance the output timing relative to the reference frame. This should be specified prior to
programming the output initialization sequence. See section Output Frame Line Offset.
Register 12h
Bits 3-0: MSBs of Line Offset for the Output Top of Frame (TOF_OFFSET)
This register contains the 4 MSBs of TOF_OFFSET. See the description for register 11h.
Bit 7-4: These bits contain zeros (non-programmable)
PLL 1, 2, 3 Charge Pump Current Control Registers
Register 13h
Bits 4-0: PLL 1 Charge Pump Current Control (ICP1)
ICP1 can be programmed to specify the charge pump current for PLL 1, which generates 27 MHz from the
VCXO output. The PLL 1 charge pump current, or I_CP1, is one of the loop gain parameters can be programmed to
set and optimize PLL 1's loop response. For more information on setting the loop response, see section LOOP
RESPONSE .
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