LMH1982SQ-NOPB Datasheet, PDF (6/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for T_A = 25°C, V_DD = 3.3V, DV_DD = 2.5V, Boldface limits apply at the
temperature extremes.
Parameter
Test Conditions
Min ⁽¹⁾
Typ ⁽²⁾
Max ⁽¹⁾
Units
t_R
Rise Time
15 pF load
1.5
ns
t_F
Fall Time
15 pF load
1.5
ns
t_{D_TOF} TOF Output Delay Time Specified for any SD or HD format
2
ns
(5)
generated from 27 MHz TOF clock ⁽⁶⁾,
outputs initialized ⁽⁷⁾, 15 pF load
Clock Outputs (Pins 19, 20, 23, 24)
Jitter_SD
27 MHz TIE Peak-to-Peak HD_CLK = Hi-Z
Output Jitter ⁽⁸⁾
HD_CLK = 74.176 MHz
23
ps
40
ps
67.5 MHz TIE Peak-to-
Peak Output Jitter ⁽⁸⁾
HD_CLK = Hi-Z
HD_CLK = 74.176 MHz
40
ps
50
ps
Jitter_HD
74.176 MHz TIE Peak-to- SD_CLK = Hi-Z
Peak Output Jitter ⁽⁸⁾
SD_CLK = 27 MHz
55
ps
65
ps
74.25 MHz TIE Peak-to-
Peak Output Jitter ⁽⁸⁾
SD_CLK = Hi-Z
SD_CLK = 27 MHz
40
ps
50
ps
148.35 MHz TIE Peak-to- SD_CLK = Hi-Z
Peak Output Jitter ⁽⁸⁾
SD_CLK = 27 MHz
60
ps
70
ps
148.5 MHz TIE Peak-to-
Peak Output Jitter ⁽⁸⁾
SD_CLK = Hi-Z
SD_CLK = 27 MHz
45
ps
55
ps
t_{D_SD}
27 MHz Output Delay
SD_CLK = 27 MHz, Any valid output
4
ns
Time ⁽⁹⁾
timing, outputs initialized ⁽⁷⁾
67.5 MHz Output Delay SD_CLK = 67.5 MHz, 525i output timing
6
ns
Time ⁽⁹⁾
(6)_{, outputs initialized} (7)
t_{D_HD} 74.176 MHz Output Delay HD_CLK = 74.176 MHz, 1080i/59 output
4.5
ns
Time ⁽¹⁰⁾
timing ⁽¹¹⁾, outputs initialized ⁽¹²⁾
74.25 MHz Output Delay HD_CLK = 74.25 MHz, 1080i/50 output
-0.6
ns
Time ⁽¹⁰⁾
timing ⁽¹¹⁾, outputs initialized ⁽¹²⁾
148.35 MHz Output Delay HD_CLK = 148.35 MHz, 1080p/59
1.5
ns
Time ⁽¹⁰⁾
output timing ⁽¹¹⁾, outputs initialized ⁽¹²⁾
148.5 MHz Output Delay HD_CLK = 148.5 MHz, 1080p/50 output
4.5
ns
Time ⁽¹⁰⁾
timing ⁽¹¹⁾, outputs initialized ⁽¹²⁾
V_OD
Differential Signal Output 100Ω differential load
Voltage ⁽¹³⁾
247
350
454
mV
(5) t_{D_TOF} is measured from the TOF pulse (leading negative edge) to the 27 MHz SD_CLK output (positive edge) using 50% levels.
(6) For any SD and HD output formats, the TOF pulse can be generated using 27 MHz as the TOF clock by programming TOF_CLK = 0,
SD_FREQ = 0, and the alternative output counter values shown in Table 1. See section HD Format TOF Generation using a 27 MHz
TOF Clock.
(7) Output initialization refers to the initial alignment of the output frame clock and TOF signals to the input reference frame. See section
Programming The Output Initialization Sequence.
(8) The SD and HD clock output jitter is based on VCXO clock (pin 29) with 20 ps peak-to-peak using a time interval error (TIE) jitter
measurement. The typical TIE peak-to-peak jitter was measured on the LMH1982 evaluation bench board using TDSJIT3 jitter analysis
software on a Tektronix DSA70604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10^-12 bit
error rate (BER), >1 Meg samples recorded using multiple acquisitions Oscilloscope Setup: 20 mV/div vertical scale, 100 µs/div
horizontal scale, and 25 GS/s sampling rate
(9) t_{D_SD} is measured from the VCXO clock input (pin 29) to the SD_CLK output (pins 23, 24) using positive edges and 50% levels. The
measurement is taken at the leading edge of the TOF pulse ⁽⁾, where the input and output clocks are phase aligned at the start of frame.
(10) t_{D_HD} is measured from the VCXO clock input (pin 29) to the HD_CLK output (pins 19, 20) using positive edges and 50% levels. The
measurement is taken at the leading edge of the TOF pulse ⁽¹¹⁾, where the input and output clocks are phase aligned at the start of
frame.
(11) For any SD and HD output formats, the TOF pulse can be generated using 27 MHz as the TOF clock by programming TOF_CLK = 0,
SD_FREQ = 0, and the alternative output counter values shown in Table 1. See section HD Format TOF Generation using a 27 MHz
TOF Clock.
(12) Output initialization refers to the initial alignment of the output frame clock and TOF signals to the input reference frame. See section
Programming The Output Initialization Sequence.
(13) This parameter is specified for the SD_CLK output only. This parameter is ensured by design for the HD_CLK output.
6
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