LMH1982SQ-NOPB Datasheet, PDF (30/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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In Free Run mode, REF_VALID will be set to 0 to indicate the absence of any input pulses at the selected HREF
port.
Bit 1: SD Clock PLL Lock Status (SD_LOCK)
SD_LOCK is a read-only bit and indicates PLL lock status of the selected SD clock. See section PLL Lock
Detection.
SD_LOCK = 0: Indicates loss of lock.
SD_LOCK = 1: Indicates valid lock.
Bit 2: HD Clock PLL Lock Status (HD_LOCK)
HD_LOCK is a read-only bit and indicates PLL lock status of the selected HD clock. See section PLL Lock
Detection.
HD_LOCK = 0: Indicates loss of lock.
HD_LOCK = 1: Indicates valid lock.
Bits 7-3: Lock Control (LOCK_CTRL)
LOCK_CTRL controls the phase error threshold of PLL 1's lock detector. A larger value for LOCK_CTRL will
yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when
lock is initially indicated, whereas a smaller value will yield the opposite effect. See section Programming the PLL
Lock Threshold.
Input Control Register
Register 02h
Bit 0: VREF_B Input Signal Polarity (POL_VB)
This bit should be programmed to match the input signal polarity at the VREF_B input pin.
POL_VB = 0: Negative polarity or active low signal.
POL_VB = 1: Positive polarity or active high signal.
Bit 1: HREF_B Input Signal Polarity (POL_HB)
This bit should be programmed to match the input signal polarity at the HREF_B input pin. The positive edge of
the output clock will be phase locked to the active edge of the H sync input signal.
POL_HB = 0: Negative polarity or active low signal.
POL_HB = 1: Positive polarity or active high signal.
Bit 2: VREF_A Input Signal Polarity (POL_VA)
This bit should be programmed to match the input signal polarity at the VREF_A input pin.
POL_VA = 0: Negative polarity or active low signal.
POL_VA = 1: Positive polarity or active high signal.
Bit 3: HREF_A Input Signal Polarity (POL_HA)
This bit should be programmed to match with the input signal polarity at HREF_A input pin. The positive edge of
the output clock will be phase locked to the active edge of the H sync input signal.
POL_HA = 0: Negative polarity or active low signal.
POL_HA = 1: Positive polarity or active high signal.
Bit 4: 27 MHz Reference Control (27M_REF)
Instead of an H sync signal, a 27 MHz clock signal can be applied to the selected HREF input to phase lock the
output clocks. If a 27 MHz clock is used as a reference, then a value of 1 should be programmed to 27M_REF,
REF_DIV_SEL, and FB_DIV.
27M_REF = 0: H sync input signal.
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