LMH1982SQ-NOPB Datasheet, PDF (36/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
TYPICAL SYSTEM BLOCK DIAGRAMS
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V_C
LOOP
FILTER
VCXO
ANALOG
REF. IN
27 MHz
LMH1981
MULTI-FORMAT VIDEO
SYNC SEPARATOR
H sync
LPF VCXO _TOF
V sync REF_A
SD_CLK
LMH1982
MULTI-RATE
CLOCK GENERATOR
TOF
27 or
67.5 MHz
GENLOCKED
3G-SDI OUT
TX
FPGA
with SerDes
TRIPLE-RATE SDI
H sync
OPTIONAL BACK-UP
REFERENCE INPUTS ^{V sync REF_B}
HD_CLK
74.25,
74.176,
148.5 or 148.35 MHz
ASYNCHRONOUS
3G-SDI IN
RX_1
WRITE/READ DATA and
TIMING/CLOCK SIGNALS
FRAME
BUFFER
Figure 15. Analog Reference Genlock for Triple-Rate SDI Video
V_C
LOOP
FILTER
VCXO
H sync
OPTIONAL BACK-UP
REFERENCE INPUTS
V sync
H sync
V sync
27 MHz
LPF VCXO _TOF
REF_A
SD_CLK
LMH1982
MULTI-RATE
CLOCK GENERATOR
TOF
27 or
67.5 MHz
REF_B
HD_CLK
74.25,
74.176,
148.5, or 148.35 MHz
GENLOCKED
3G-SDI OUT
TX
FPGA
with SerDes
TRIPLE-RATE SDI
RX_1
RX_2
ASYNCHRONOUS
3G-SDI IN
SDI REF. IN
WRITE/READ DATA and
TIMING/CLOCK SIGNALS
RECOVERED SYNC TIMING
FROM SDI REF. IN
FRAME
BUFFER
Figure 16. SDI Reference Genlock for Triple-Rate SDI Video
36
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