LMH1982SQ-NOPB Datasheet, PDF (27/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
I²C INTERFACE PROTOCOL
The protocol of the I²C interface begins with the start pulse followed by a byte comprised of a seven-bit slave
device address and a read/write bit as the LSB. Therefore, the address of the LMH1982 for write sequences is
DCh (1101 1100) and the address for read sequences is DDh (1101 1101). Figure 12, Figure 13, and Figure 14
show a write and read sequence across the I²C interface.
Write Sequence
The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is held
high. The slave device address is sent next. The address byte is made up of an address of seven bits (7:1) and
the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an
acknowledge (ACK) bit. When SCL is high the master will release the SDA line. The slave must pull SDA low to
acknowledge. The address of the register to be written to is sent next. Following the register address and the
ACK bit, the data byte for the register is sent. When more than one data byte is sent, it is automatically
incremented into the next address location. See Figure 12. Note that each data byte is followed by an ACK bit.
Figure 12. LMH1982 Write Sequence
Read Sequence
Read sequences are comprised of two I₂C transfers. The first is the address access transfer, which consists of a
write sequence that transfers only the address to be accessed. The second is the data read transfer, which starts
at the address accessed in the first transfer and increments to the next address per data byte read until a stop
condition is encountered.
The address access transfer shown in Figure 13 consists of a start pulse, the slave device address including the
read/write bit (a zero, indicating a write), then its ACK bit. The next byte is the address to be accessed, followed
by the ACK bit and the stop bit to indicate the end of the address access transfer.
The subsequent read data transfer shown in Figure 14 consists of a start pulse, the slave device address
including the read/write bit (a one, indicating a read) and the ACK bit. The next byte is the data read from the
initial access address. Subsequent read data bytes will correspond to the next increment address locations. Each
data byte is separated from the other data bytes by an ACK bit.
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 A0
S ^110111000
t
a
r
I²C
WA
rC
t
Slave
IK
Address
t
$DC
e
Address
0S
t
Ao
Cp
K
Figure 13. LMH1982 Read Sequence – Address Access Transfer
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