LMH1982SQ-NOPB Datasheet, PDF (22/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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To ensure that the output clock and TOF pulse are properly aligned and subsequently phase locked to the
reference frame, the output initialization sequence should be programmed accordingly.
During the output frame immediately prior to the frame the initialization is to occur:
1. Set EN_TOF_RST = 1(register 0Ah) to enable output alignment mode.
2. Toggle TOF_INIT (register 0Ah) from 0 to 1 to reset the internal counters. On the next frame, the output
clock and TOF pulse will be initialized (aligned) to the reference frame with line offset programmed to
TOF_OFFSET.
3. Immediately after the initialization and before the next output frame occurs, clear EN_TOF_RST and
TOF_INIT to 0. Otherwise, the output clock will be continually aligned on every output frame while
EN_TOF_RST = 1. Continual alignment which may cause excessive jitter on the output clock (from PLL 2, 3,
or 4) due to slight differences in the delay paths of the internal logic. This occurrence of excessive clock jitter
can be avoided by disabling output alignment mode (EN_TOF_RST = 0) immediately after the initialization
sequence.
TOF Output Delay Considerations
Due to the following conditions, the TOF pulse may be delayed or offset by more than one TOF clock period
(t_{D_TOF} > 1 pixel) even after output initialization:
1. The delay paths of the internal logic used to generate and align the TOF pulse is greater than one period of
the TOF clock. This can occur for HD format TOF pulses generated using the 148 MHz native pixel clock.
For HD format TOF generation, it is recommended to use the 27 MHz SD clock as the TOF clock instead of
the native HD pixel clock as shown in section Output Frame Timing.
2. The H sync and/or V sync input pulses have excessive jitter equal to or larger than half of a pixel period of
the selected output clock. Input sync jitter less than 3 ns peak-to-peak is recommended.
3. PLL 1 is not completely phase locked or stable when the output initialization is performed. The VCXO clock
phase error with respect to the H sync input should less than one period of the selected TOF clock.
Output Clock Initialization without TOF
For applications that do not require the TOF pulse, it is still necessary to program all output format registers prior
to the output initialization sequence. This is because the output initialization circuitry relies on the full and correct
specification of the output format. If the TOF output is not needed, it can be put in Hi-Z mode by setting TOF_HIZ
= 1 (register 08h).
Output Behavior Upon Loss Of Reference
After loss of reference (LOR), the LMH1982 will maintain the TOF pulse without the input reference according to
the terminal counts of the reference clock; however, output frequency accuracy will be determined by the VCXO,
which may be in Free Run or Holdover operation.
To disable output alignment to an arbitrary reference frame when the reference is reapplied, set EN_TOF_RST =
0 before the reference returns. After PLL 1 has re-locked to the reference, the outputs can be initialized to the
desired reference frame.
REFERENCE AND PLL LOCK STATUS
The LMH1982 features a reference detector and PLL lock detector that can be used to indicate genlock status of
the input reference and device PLLs. Genlock status can be sampled via the NO_REF and NO_LOCK status flag
output pins and the REF_VALID, SD_LOCK, and HD_LOCK status bits (register 01h). Both the reference and
PLL lock detectors may be programmed for their respective detection thresholds according to the needs of the
application system. See Table 7 for a summary of the genlock status bits and status outputs for different
conditions.
The NO_REF and NO_LOCK outputs are derived from the genlock status bits and given by the following two
logic equations:
NO_REF = REF_VALID
NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK)
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