LMH1982SQ-NOPB Datasheet, PDF (24/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the
expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the
opposite effect.
PLL Lock Status Instability
It is possible for excessive jitter on the H input to indicate lock instability through the NO_LOCK output, even if
the VCXO and output clocks are properly phase locked and no system-level errors are occurring (e.g. bit errors).
To reduce the probability of false loss of lock indication or lock status instability, LOCK_CTRL can be increased
to improve the lock detector’s ability to tolerate a larger amount of input phase jitter or phase error. This can help
to ensure the NO_LOCK output and SD_LOCK bit are stable when the reference signal has large input jitter.
Table 7. Summary of Genlock Status Bits and Flag Outputs⁽¹⁾
Conditions
Genlock mode,
Reference valid,
PLLs locking
Genlock mode,
Reference valid,
PLLs locked
Genlock mode,
Reference lost,
Free Run operation
Genlock mode,
Reference lost,
Holdover operation
Mode Control Bits
Register 00h
GNLK HOLD-OVER
Status Flag Outputs
NO_REF ¹ NO_LOCK ²
(pin 16)
(pin 17)
1
X
0
1
HD_LOCK
bit 2
0
Status Bits
Register 01h
SD_LOCK
bit 1
0
1
X
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
0
(1) Status flag output logic equations:
1. NO_REF = REF_VALID
2. NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK)
REF_VALID
bit 0
1
1
0
0
LOOP RESPONSE
The overall loop response of the LMH1982 is determined by the design of the VCXO PLL (PLL 1). Because the
integrated VCO PLLs use the VCXO clock as the input reference to phase lock the output clocks, the ability of
PLL 1 to attenuate the input jitter is critical to output jitter performance, especially low-frequency jitter that occurs
at the video line and field rates. The loop response of the LMH1982 can be characterized by PLL 1's loop
bandwidth and damping factor.
The loop response is primarily determined by the loop filter components and the loop gain. A passive second-
order loop filter consisting of R_S, C_S, and C_P components can provide sufficient input jitter attenuation for most
applications, although a higher order passive filter or active filter may also be used. The loop gain is a function of
the VCXO gain and programmable PLL parameters.
A lower loop bandwidth will provide higher input jitter attenuation (reduced jitter transfer) for improved output jitter
performance; however, increased lock time (or settling time) and larger external component values are a couple
trade-offs to a lower loop bandwidth.
Loop Response Design Equations
The following equations can be used to design the loop response of PLL 1.
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