LMH1982SQ-NOPB Datasheet, PDF (17/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
SD_CLK (MHz)
27
67.5
Table 4. SD Clock Frequency Selection
SD_FREQ
Register 08h
0
1
PLL#
1
4
The HD clock frequency can be selected from Table 5 and programmed to HD_FREQ (register 08h). PLL 2 and
PLL 3 are used to generate the four different HD clock rates but only one HD clock can be selected at a time. If
the HD_CLK output is not needed, it can be put in Hi-Z mode by setting HD_HIZ = 1 (register 08h).
NOTE
If 148.35 MHz is selected, it is required to follow the programming sequence described in
section 148.35 MHz PLL Initialization Sequence.
HD_CLK (MHz)
74.25
74.25/1.001
148.5
148.5/1.001
Table 5. HD Clock Frequency Selection
HD_FREQ
Register 08h
0h
1h
2h
3h
PLL#
2
3
2
3
Programming The Output Format Timing
When PLL 1 is stable and locked to the input reference, the output format timing should be specified. The
functional block diagram for TOF generation and output initialization is shown in Figure 9.
For proper output generation and initialization, the reference format and output format timings must be fully and
correctly programmed to the output format registers 09h–12h, which specify the following:
• Output TOF Clock
• Output Frame Timing
• Reference Frame Timing
• Input-Output Frame Rate Ratio
• Output Frame Line Offset
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