LMH1982SQ-NOPB Datasheet, PDF (28/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
www.ti.com
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S ^110111010
0
0S
t
t
a
r
I²C
RA
eC
Data Byte 1
A
C
Data Byte n
Ao
Cp
t
Slave
aK
K
K
Address
d
$DD
Figure 14. LMH1982 Read Sequence – Data Read Transfer
I²C Enable Control Pin
When the active low input I2C_ENABLE = 0, the LMH1982 will enable I²C communication via its fixed slave
address; otherwise, the LMH1982 will not respond. For applications with multiple LMH1982 devices on the same
I²C bus, the I²C enable function can be useful for writing data to a specific device(s) and for reading data from an
individual device to prevent bus contention. For single chip applications, the I2C_ENABLE input can be tied to
GND to keep the I²C interface enabled.
I²C INTERFACE CONTROL REGISTER DEFINITIONS
Table 8. I²C Interface Control Register Map⁽¹⁾
Register
Address
00h
Default
Data
A3h
01h
86h
02h
00h
03h
01h
04h
B4h
05h
06h
06h
00h
07h
00h
08h
04h
09h
01h
0Ah
00h
0Bh
B4h
0Ch
06h
0Dh
0Dh
0Eh
02h
0Fh
0Dh
10h
02h
11h
00h
12h
00h
13h
88h
14h
88h
D7
GNLK_I²C
RSV
RSV
0
RSV
RSV
RSV
EN_TOF_
RST
0
0
0
0
RSV
D6
D5
D4
D3
D2
D1
D0
GNLK
RSEL_I²C
RSEL
HOLD-
OVER
H_ERROR [2:0]
LOCK_CTRL [7:3]
HD_LOCK SD_LOCK REF_VALID
RSV
PIN6_
OVRD
REF_27
POL_HA
POL_VA
POL_HB
POL_VB
RSV
RSV
RSV
RSV
RSV
REF_DIV_SEL [1:0]
FB_DIV [7:0]
0
0
FB_DIV [12:8]
RSV
RSV
RSV
ICP4 [3:0]
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
TOF_HIZ
HD_HIZ
HD_FREQ [3:2]
SD_HIZ
SD_FREQ
TOF_RST [7:0]
POL_TOF TOF_INIT
TOF_RST [12:8]
0
TOF_CLK
0
0
0
0
0
0
RSV
RSV
ICP2 [7:4]
TOF_PPL [7:0]
TOF_LPFM [7:0]
0
REF_LPFM [7:0]
0
TOF_OFFSET [7:0]
0
TOF_PPL [12:8]
TOF_LPFM [11:8]
REF_LPFM [11:8]
TOF_OFFSET [11:8]
ICP1 [4:0]
ICP3 [3:0]
(1) When writing to registers containing reserved bits (RSV), make sure the RSV bits are programmed with their original default data shown
in column 2 of Table 8; otherwise, improper device operation may result.
28
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