LMH1982SQ-NOPB Datasheet, PDF (23/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Reference Detection
In Genlock mode, a valid reference will be indicated by NO_REF = 0 when all the criteria below are met.
Otherwise, a loss of reference (LOR) will be indicated by NO_REF = 1.
• An H sync signal is applied to the input reference and conforms to one of the standard formats in Table 1. A
V sync signal is not used in reference detection.
• The PLL divide registers are programmed according to the input reference format.
• The control voltage of the VCXO is not within about 500 mV of the GND or V_DD supplies.
Programming the Loss of Reference (LOR) Threshold
The reference detector's error threshold can be programmed to H_ERROR (register 00h), which determines the
maximum number of missing H sync pulses before indicating an LOR. The LOR threshold will be the H_ERROR
value multiplied by the PLL 1 reference divider value, as shown in Table 6.
REF_DIV_SEL
Register 03h
0h
1h
2h
Table 6. LOR Threshold Selection
Reference Divider
2
1
5
LOR Threshold
2 x H_ERROR
1 x H_ERROR
5 x H_ERROR
If H_ERROR = 0, then the device will react after the first missing pulse. When the LOR threshold is exceeded,
the NO_REF output will indicate LOR, and the device will default to either Free Run or Holdover operation for as
long as the reference is lost. As the LOR threshold value is increased, the accuracy for counting the actual
number of missing H pulses may diminish due to frequency drifting by PLL 1.
NOTE
If the input reference is missing H pulses periodically, e.g. every vertical interval period,
the PLL may not indicate a valid reference nor achieve lock regardless of the H_ERROR
value programmed. This is because periodically missing pulses will translate to a lower
average frequency than expected. When the average input frequency falls outside of the
absolute pull range (APR) of the VCXO, the PLL will not be able to frequency lock to the
input reference.
PLL Lock Detection
In Genlock mode, PLL lock will be indicated by NO_LOCK = 0 when all the criteria below are met. Otherwise, a
loss of lock will be indicated by NO_LOCK = 1.
• A valid reference is indicated (REF_VALID = 1).
• PLL 1 or PLL 4 is phase locked to the input reference (SD_LOCK = 1).
• PLL 2 or PLL 3 is phase locked to the VCXO clock reference (HD_LOCK = 1).
PLLs 2, 3, and 4 have high loop bandwidths, which allow them to achieve lock quickly and concurrently while
PLL 1 achieves lock. Because PLL 1 has a much lower loop bandwidth, it will dictate the overall lock indication
time.
Programming the PLL Lock Threshold
PLL 1's lock detector threshold can be programmed to LOCK_CTRL (register 01h), which determines the
maximum phase error between PLL 1's phase detector (PD) inputs before indicating an unlock or lock condition.
The PD inputs are the reference signal (H sync input / reference divider) and the feedback signal (VCXO clock /
feedback divider).
The lock detector will indicate loss of lock when the phase error between the PD inputs is greater than the lock
threshold for three consecutive phase comparison periods. Conversely, it will indicate valid lock when the phase
error is less than the lock threshold for three consecutive phase comparison periods.
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