LMH1982SQ-NOPB Datasheet, PDF (5/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
Operating Ratings
V_DD
DV_DD
Input Voltage
Temperature Range, T_A
SNLS289C – APRIL 2008 – REVISED MARCH 2013
3.3V ± 5%
2.5V ± 5%
0V to V_DD
0°C to 70°C
Electrical Characteristics
Unless otherwise specified, all limits are specified for T_A = 25°C, V_DD = 3.3V, DV_DD = 2.5V, Boldface limits apply at the
temperature extremes.
Parameter
Test Conditions
Min ⁽¹⁾
Typ ⁽²⁾
Max ⁽¹⁾
Units
I_VDD
V_DD Supply Current
Default register settings, no input
47
mA
I_DVDD
DV_DD Supply Current
reference, 27 MHz VCXO and loop filter
connected, 100Ω differential load on
39
mA
SD_CLK and HD_CLK outputs; no load
on all other outputs
I_VDD
I_DVDD
V_DD Supply Current
DV_DD Supply Current
V_DD = 3.465V, DV_DD = 2.75V, Genlock
mode, 1080p/59 output timing, HD_CLK
= 148.35 MHz, SD_CLK = 67.5 MHz,
100Ω differential load on SD_CLK and
HD_CLK outputs; no load on all other
outputs
57
70
mA
44
60
mA
Free Run Voltage Control Input (Pin 1)
V_IL
Low Analog Input Voltage ⁽³⁾
V_IH
High Analog Input Voltage ⁽³⁾
Reference Inputs (Pins 4, 5, 7, 8)
0
V
V_DD
V
V_IL
V_IH
ΔT_HV
Low Input Voltage
High Input Voltage
H-V Sync Timing Offset
I_IN = ±10 μA
I_IN = ±10 µA
Input timing offset measured from H
sync to V sync pulse leading edges ⁽⁴⁾
0
0.7 V_DD
0.3 V_DD
V
V_DD
V
2.0
μs
Digital Control Inputs (Pins 6, 13, 14, 15)
V_IL
Low Input Voltage
V_IH
High Input Voltage
I²C Interface (Pins 11, 12)
I_IN = ±10 µA
I_IN = ±10 µA
0
0.7 V_DD
0.3 V_DD
V
V_DD
V
V_IL
Low Input Voltage
V_IH
High Input Voltage
I_IN
Input Current
I_OL
Low Output Sink Current
Status Flag Outputs (Pin 16, 17)
V_IN between 0.1 V_DD and 0.9 V_DD
V_OL = 0V or 0.4V
0
0.7 V_DD
−10
0.3 V_DD
V
V_DD
V
+10
μA
3
mA
V_OL
Low Output Voltage
V_OH
High Output Voltage
Top of Frame Output (Pin 25)
I_OUT = +10 mA
I_OUT = −10 mA
V_DD −0.4V
0.4
V
V
V_OL
Low Output Voltage
I_OUT = +10 mA
0.4
V
V_OH
High Output Voltage
I_OUT = −10 mA
V_DD −0.4V
V
I_OZ
Output Hi-Z Leakage
Current
TOF output in Hi-Z mode, output pin
connected to V_DD or GND
0.4
10
|μA|
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be
clean from noise that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run
operation.
(4) ΔT_HV is a required specification that allows for proper frame decoding and subsequent output initialization (alignment). For interlace
formats, the H-V sync timing offset must be within ΔT_HV for all even fields and be outside ΔT_HV for odd fields. For progressive formats,
the H-V sync timing offset must be within ΔT_HV for all frames. See sections Reference Frame Decoder and Output Frame Line Offset.
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