LMH1982SQ-NOPB Datasheet, PDF (16/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
www.ti.com
Some supported input formats in Table 1 have two sets of compatible divider values: reduced dividers and non-
reduced dividers. See Examples 2A and 2B below. Because the loop response of PLL 1 is dependent on the
feedback divider value, a lower loop bandwidth and phase comparison frequency can be achieved by
programming the non-reduced divider set (see LOOP RESPONSE ).
Examples:
1) For 1080i/59.94 input reference, the dividers are:
• Reference divider = 5 (REF_DIV_SEL = 2h)
• Feedback divider = 4004 (FB_DIV = FA4h)
2A) For 1080i/50 input reference, the reduced dividers are:
• Reference divider = 1 (REF_DIV_SEL = 1h)
• Feedback divider = 960 (FB_DIV = 3C0h)
2B) For 1080i/50 input reference, the non-reduced (alternative) dividers are:
• Reference divider = 5 (REF_DIV_SEL = 2h)
• Feedback divider = 4800 (FB_DIV = 12C0h)
Reference Frame Decoder
The LMH1982 features an internal frame decoder to determine the reference frame timing from only the H and V
sync input timing, which eliminates an extra input pin for an odd/even field timing. The reference frame timing is
required to allow for output frame initialization (output TOF and clock alignment) to the reference frame.
To allow for proper frame decoding and subsequent output initialization, the H sync and V sync inputs must
comply with the H-V sync timing offset specification, ΔT_HV. For interlace formats, the H-V sync timing offset must
be within ΔT_HV for even fields and be outside ΔT_HV for odd fields. Compliance with this specification will ensure
the internal frame counters are reset only once per frame. For progressive formats, the H-V timing offset must be
within ΔT_HV for all frames.
Since the LMH1982 was designed for compatibility with the LMH1981 sync separator, its H and V sync pulses
will comply with the ΔT_HV specification for any input reference format.
For digital timing from an FPGA SDI deserializer, the recovered H and V sync pulses may be co-timed and be
within ΔT_HV for both odd and even fields. This will cause the internal frame counters to reset twice per frame and
thus preclude proper frame decoding and output initialization. As a simple work-around, the designer may
choose to configure the FPGA to gate the V sync signal, allowing only the even field V pulses and gating off the
odd field V pulses.
OUTPUT CLOCKS AND TOF
The LMH1982 has simultaneous LVDS output SD and HD clocks and an output TOF pulse. For proper output
format timing generation and subsequent output initialization, it is highly recommended to follow the programming
sequence below:
1. Program the output clock frequencies (section Programming The Output Clock Frequencies).
2. Program the output format timing (section Output Frame Timing).
3. Program the output initialization sequence (section Programming The Output Initialization Sequence).
Programming The Output Clock Frequencies
The SD clock frequency can be selected from Table 4 and programmed to SD_FREQ (register 08h). PLL 1 and
PLL 4 are used to generate the two SD clock rates but only one SD clock can be selected at a time. If the
SD_CLK output is not needed, it can be put in Hi-Z mode by setting SD_HIZ = 1 (register 08h).
If 27 MHz is selected, the VCXO clock is directly converted from a 3.3V single-ended clock at the VCXO input
(pin 29) to an LVDS clock at the SD_CLK output port (pins 23 and 24). If 67.5 MHz is selected, the VCXO clock
is used as an input reference for PLL 4 to generate this SD clock frequency. In some FPGA SD-SDI SerDes
applications, the 67.5 MHz frequency may be required as an SD reference clock instead of the standard 27 MHz
frequency.
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