LMH1982SQ-NOPB Datasheet, PDF (31/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
27M_REF = 1: 27 MHz clock input signal. Also, set REF_DIV_SEL =1 and FB_DIV = 1
NOTE
Because the loop gain, K, for 27 MHz clock input is much larger than for an H sync input
(due to the large difference in FB_DIV), the loop filter design will be necessarily different
between the 27 MHz input and H sync inputs. Alternatively, it's possible to use an external
counter circuit to divide the 27 MHz clock to a lower frequency (e.g. like H sync) input, so
only one loop filter design could support both types of inputs.
Bit 5: Pin 6 Override (PIN6_OVRD)
The PIN6_OVRD bit can be programmed to override the default reference selection capability on pin 6 and
instead use pin 6 as an logic pulse input to initialize or reset the internal counters for output initialization.
PIN6_OVRD = 0: Allows a logic level input to be applied to pin 6 for reference selection if RSEL_I²C = 0
(register 00h). If RSEL_I²C = 1, then pin 6 is ignored and reference selection is controlled via I²C; additionally,
outputs must be initialized via I²C by programming TOF_INIT and EN_TOF_RST (register 0Ah).
PIN6_OVRD = 1: Allows an TOF Init pulse to be applied to pin 6 for output initialization if EN_TOF_RST = 1. If
EN_TOF_RST = 0, then any TOF Init pulse received at pin 6 will be ignored. Additionally, reference selection
must be controlled via I²C, regardless of I²C_RSEL.
Bits 7-6: Reserved (RSV)
These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as
specified in Table 8.
PLL 1 Divider Register
Register 03h
Bits 1-0: Reference Divider Selection (REF_DIV_SEL)
REF_DIV_SEL selects the reference divider value according to the selection table in Table 2. See section
Programming the PLL 1 Dividers.
The reference divider value is the denominator of PLL 1's divider ratio:
Feedback divider value / Reference divider value = 27 MHz / Hsync input frequency
The numerator and denominator values of the divider ratio should be reduced to their lowest factors to be
compatible with the range of divider values offered by REF_DIV_SEL and FB_DIV. These registers must be
programmed correctly to phase lock the 27 MHz VCXO PLL and output clocks to the input reference. See
Table 1 for the suggested divider settings for the supported timing formats.
Bits 7-3: Reserved (RSV)
These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as
specified in Table 8.
Register 04h
Bits 7-0: Feedback Divider (FB_DIV)
This register contains the 8 LSBs of FB_DIV. The feedback divider value is the numerator of PLL 1's divider
ratio. FB_DIV should be programmed using the feedback divider value after the divide ratio has been reduced to
its lowest factors. Refer to the description for register 03h, and see Table 1 for the suggested divider settings for
the supported timing format.
Register 05h
Bits 4-0: Feedback Divider (FB_DIV)
This register contains the 5 MSBs of FB_DIV. See the description for register 04h.
Bits 7-5: These non-programmable bits contain zeros.
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