LMH1982SQ-NOPB Datasheet, PDF (26/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
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Loop Response Optimization Tips
The need to support various input reference formats will usually require a diverse range of PLL divider values,
which can each yield a different loop response assuming all other PLL parameters are kept the same. Typically,
it is desired to design and optimize the loop response across all supported input formats without modification to
the loop filter circuit. This requires that the loop gain, K, be kept constant across all supported divider values
because K affects both BW and DF equations. To keep a narrow range for K, the ratio (I_CP1 / feedback divider)
should be kept relatively constant. This can be achieved by programming ICP1, so that I_CP1 is scaled with
FB_DIV for each supported input format.
It is suggested to start designing the loop filter component values from the BW and DF equations with initial
assumptions of FB_DIV = 1716 (NTSC) and I_CP1 = 250 µA (default setting). Once reasonable component values
are achieved under these initial assumptions, it is necessary to check that K can be maintained over the
expected range of FB_DIV by adjusting I_CP1. The usable current range of I_CP1 is limited to a practical minimum of
94 µA (ICP1 = 3d) to a maximum of 969 µA (ICP1 = 31d), which should provide adequate range to maintain a
narrow range for K assuming the suggested initial values for FB_DIV and I_CP1 were followed. If a narrow range
for K cannot be maintained within the usable range of I_CP1, then the loop filter design may need to be modified.
Some trial-and-error and iterative calculations may be necessary to find an optimal loop filter.
In some loop filter designs, the calculated I_CP1 current that is required for a target K value may be near or below
the practical minimum of the I_CP1 current range. In this scenario, it may also be possible to leverage the
programmable reference and feedback dividers by scaling up the values in proportion (i.e. same reduced divider
ratio). This would allow I_CP1 to be scaled up by the same proportion to be within the usable I_CP1 current range
and maintain the same K value, since I_CP1 and FB_DIV would be scaled by the same factor. For example, by
scaling the divider values by a factor of 5x, I_CP1 can also be scaled up by 5x such that its within the usable
current range. This technique of scaling FB_DIV and I_CP1 assumes that the input format has an alternative set of
compatible divider values as shown in Table 1.
Loop Filter Capacitors
It is suggested to use tantalum capacitors for C_S and C_P instead of ceramic capacitors in the PLL loop filter,
which is a sensitive analog circuit. Ferroelectric ceramics, such as X7R, X5R, Y5V, Y5U, etc., exhibit
piezoelectric effects that generate electrical noise in response to mechanical vibration and shock. This electrical
noise can modulate the VCXO control voltage and consequently induce clock jitter at high amplitudes when the
board and ceramic components are subjected to vibration or shock. Tantalum capacitors can be used to mitigate
this effect.
Lock Time Considerations
The LMH1982 lock time or settling time is determined by the loop response of PLL 1, which has a much lower
loop bandwidth compared to the integrated PLLs used to derive the other output clock frequencies. Generally,
the lock time is inversely proportional to the loop bandwidth; however, if the loop response is not designed or
programmed for sufficient PLL stability, the lock time may not be predicted from the loop bandwidth alone.
Therefore, any parameter that affects the loop response can also affect the overall lock time.
One way to reduce lock time is to widen the loop bandwidth by programming a larger or maximum value for I_CP1
while PLL 1 is locking; after PLL 1 is locked, I_CP1 can be reduced to provide a narrower loop bandwidth while
maintaining a reasonable damping factor.
VCXO Considerations
The recommended VCXO manufacturer part number is CTS 357LB3C027M0000, which has an absolute pull
range (APR) of ±50 ppm and operating temperature range of -20°C to +70°C. A VCXO with a tighter APR can
provide better output frequency accuracy in Free Run operation; however, the APR must be wider than the
worst-case input frequency error in order to achieve phase lock.
Free Run Output Jitter
The input voltage to VC_FREERUN (pin 1) should have sufficient filtering to minimize noise over the frequency
bands of interest (i.e. SMPTE SDI jitter frequency bands) which can cause VCXO input voltage modulation and
thus free run output clock jitter.
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