LMH1982SQ-NOPB Datasheet, PDF (37/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

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LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
V_C
LOOP
FILTER
VCXO
UNUSED
INPUTS
27 MHz
H sync
LPF VCXO _TOF
V sync REF_A
SD_CLK
LMH1982
MULTI-RATE
CLOCK GENERATOR
TOF
27 or
67.5 MHz
LOOPED
3G-SDI OUT
TX
FPGA
with SerDes
TRIPLE-RATE SDI
H sync
V sync REF_B
HD_CLK
74.25,
74.176,
148.5 or 148.35 MHz
3G-SDI IN
RX_1
RECOVERED SYNC TIMING
FROM 3G-SDI IN
Figure 17. Triple-Rate SDI Loop-through
LOOP ^VC
FILTER
VCXO
ANALOG
REF. IN (1)
27 MHz
LMH1981
MULTI-FORMAT VIDEO
SYNC SEPARATOR
H sync
V sync
LPF VCXO TOF
REF_A
SD_CLK
LMH1982
MULTI-RATE
CLOCK GENERATOR
TOF
27 or
67.5 MHz
H sync
V sync REF_B
HD_CLK
74.25,
74.176,
148.5 or 148.35 MHz
GENLOCKED 3G-SDI OUT (1,2)
or
LOOPED 3G-SDI OUT (3)
TX
FPGA
with SerDes
TRIPLE-RATE SDI
RX_1
RX_2
3G-SDI IN (1,2,3)
SDI REF. IN (2)
FRAME
BUFFER*
APPLICATION KEY
(1) VIDEO FOR ANALOG GENLOCK
(2) VIDEO FOR SDI GENLOCK
(3) VIDEO FOR SDI LOOP-THROUGH
RECOVERED SYNC TIMING FROM
SDI REF. IN (2) or 3G-SDI IN (3)
* FOR GENLOCK APPLICATION (1,2)
Figure 18. Combined Genlock or Loop-Through for Triple-Rate SDI Video
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