LMH1982SQ-NOPB Datasheet, PDF (2/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Typical Video Genlock Block Diagram
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V_C
LOOP
FILTER
VCXO
ANALOG
REF. IN
27 MHz
LMH1981
H sync
MULTI-FORMAT VIDEO _{V sync REF_A}
SYNC SEPARATOR
LPF VCXO TOF
SD_CLK
LMH1982
MULTI-RATE
CLOCK GENERATOR
TOF
27 or
67.5 MHz
GENLOCKED
3G-SDI OUT
TX
FPGA
with SerDes
TRIPLE-RATE SDI
H sync
OPTIONAL BACK-UP
REFERENCE INPUTS ^{V sync REF_B}
HD_CLK
74.25,
74.176,
148.5 or 148.35 MHz
ASYNCHRONOUS
3G-SDI IN
RX_1
WRITE/READ DATA and
TIMING/CLOCK SIGNALS
FRAME
BUFFER
Functional Block Diagram
VC_FREERUN
GENLOCK
HREF_A
VREF_A
HREF_B
VREF_B
SWITCH
REFERENCE
SELECTION
H
and
INPUT
V
POLARITY
REF_SEL
LOOP
FILTER
LPF
27 MHz
VCXO
VCXO
PLL 1 with
EXT. VCXO
and LPF
27 MHz
27
67.5
PLL 2,3,4
with
INTEGRATED
VCOs
74.176
148.35
74.25
148.5
MUX
MUX
REFERENCE
DETECT
3
PLL LOCK
DETECT
OUTPUT
RESET
TOF
CLK
H _{OUTPUT TOF}
TIMING
V GENERATION
LVDS
LVDS
SD_CLK
SD_CLK
HD_CLK
HD_CLK
TOF_OUT
I²C INTERFACE and CONTROL REGISTERS
NO_LOCK
NO_REF
SDA SCL _I²_{C_ENABLE} RESET
2
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