LMH1982SQ-NOPB Datasheet, PDF(32/43 Page) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

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LMH1982SQ-NOPB Datasheet, PDF (32/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

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LMH1982

SNLS289C â APRIL 2008 â REVISED MARCH 2013

www.ti.com

PLL 4 Charge Pump Current Control Register

Bits 3-0: Charge Pump Current Control for PLL 4 (ICP4)

ICP4 can be programmed to specify charge pump current for PLL 4, which generates the 67.5 MHz SD clock.

NOTE

Bit 3 is inverted internally, so the default ICP4 value of 0000b (0h) actually yields an

effective value of 1000b (8h), which is the mid-scale setting.

The PLL 4 charge pump current increases linearly with the effective value. Reducing the effective value of the

charge pump current will lower its loop bandwidth at the expense of reduced PLL stability. An effective value of 0

(ICP4 = 1000b) should not be programmed since this corresponds to 0 ÂµA nominal current and will cause PLL 4

to lose phase lock.

Bits 7-4: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as

specified in Table 8.

Bits 7-0: Reserved (RSV)

This register is reserved. If necessary, only write the default data (00h) to register 07h as specified in Table 8.

Output Clock And TOF Control Register

Bit 0: SD Clock Output Frequency Select (SD_FREQ)

This bit sets the clock frequency of the SD_CLK output pair.

SD_FREQ = 0: Selects 27 MHz from PLL 1.

SD_FREQ = 1: Selects 67.5 MHz from PLL 4.

Bit 1: SD Clock Output Mode (SD_HIZ)

Set the SD_HIZ bit to 1 to put the SD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the SD_CLK

output will be enabled.

Bit 3-2: HD Clock Output Frequency Select (HD_FREQ)

These bits set the clock frequency of the HD_CLK output pair.

HD_FREQ = 0h: Selects 74.25 MHz from PLL 2.

HD_FREQ = 1h: Selects 74.176 MHz from PLL 3.

HD_FREQ = 2h: Selects 148.5 MHz from PLL 2.

HD_FREQ = 3h: Selects 148.35 MHz from PLL 3.

NOTE

When selecting the 148.35 MHz clock, you must also program the PLL 3 initialization

sequence as described in section 148.35 MHz PLL Initialization Sequence.

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