LMH1982SQ-NOPB Datasheet, PDF (33/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Bit 4: HD Clock Output Mode (HD_HIZ)
Set the HD_HIZ bit to 1 to put the HD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the HD_CLK
output will be enabled.
Bit 5: Top of Frame Output Mode (TOF_HIZ)
Set the TOF_HIZ bit to 1 to put the TOF output pin in high-impedance (Hi-Z) mode; otherwise, the output will be
enabled.
Bits 7-6: Reserved (RSV)
These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as
specified in Table 8.
TOF Configuration Registers
Register 09h
Bits 7-0: TOF Reset (TOF_RST)
This register contains the 8 LSBs of TOF_RST. When PLL 1 is phase locked to the reference, both H sync and V
sync inputs are used to reset the frame-based counters used for output TOF generation. The numerator value of
the reduced frame rate ratio should be programmed to TOF_RST. See section Input-Output Frame Rate Ratio.
Once TOF_RST is programmed, the outputs must be properly initialized by either programming TOF_INIT or
otherwise using an external TOF Init pulse (when PIN6_OVRD = 1).
Register 0Ah
Bits 4-0: TOF Reset (TOF_RST)
This register contains the 5 MSBs of TOF_RST. See the description for register 09h.
Bit 5: Output Initialization (TOF_INIT)
After enabling output alignment mode (EN_TOF_RST = 1), the TOF_INIT bit should be programmed to reset the
internal counters and initialize (align) the outputs to the desired reference frame. The output initialization is
triggered by programming a positive bit transition (0 to 1) to TOF_INIT. See section Programming The Output
Initialization Sequence.
Bit 6: TOF Pulse Output Polarity (POL_TOF)
This bit should be programmed to the desired TOF pulse polarity at the TOF output.
POL_TOF = 0: Negative polarity or active low signal.
POL_TOF = 1: Positive polarity or active high signal.
Bit 7: Output Alignment Mode (EN_TOF_RST)
This bit must be set (EN_TOF_RST = 1) to enable output alignment mode prior to initialization per section
Programming The Output Initialization Sequence. It is recommended to clear this bit (EN_TOF_RST = 0)
immediately after the output initialization sequence has been programmed to prevent excessive output jitter, as
described in section Output Disturbance While Output Alignment Mode Enabled.
Register 0Bh
Bits 7-0: Total Pixels per Line for the Output Format (TOF_PPL)
This register contains the 8 LSBs of TOF_PPL. TOF_PPL should be programmed with total pixels per line for the
desired output format. TOF_PPL is used in specifying the output frame rate. This should be specified prior to
programming the output initialization sequence. See section Output Frame Timing.
Register 0Ch
Bits 4-0: MSBs of Total Pixels per Line for the Output Format (TOF_PPL)
This register contains the 5 MSBs of TOF_PPL. See the description for register 0Bh.
Bit 5: Output Clock Select for Output Top of Frame (TOF_CLK)
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH1982
Submit Documentation Feedback
33