LMH1982SQ-NOPB Datasheet, PDF (21/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
Example:
If the input reference is 525i with a frame rate of 30/1.001 Hz and the output format is 625i with a frame rate of
25 Hz, then:
Frame rate ratio = (30/1.001) / 25 = 1200 / 1001
Therefore, the numerator, 1200, should be programmed to TOF_RST.
Output Frame Line Offset
The output clock and TOF pulse can be aligned to any line of the reference frame by programming
TOF_OFFSET (register 11h-12h) and subsequently programming the output initialization sequence. The line
offset value should be directly programmed to TOF_OFFSET to delay or advance the outputs' alignment relative
to the decoded reference frame timing (see section Reference Frame Decoder).
The TOF_OFFSET value must be greater than zero but less than or equal to the programmed value for
REF_LPFM (i.e. 0 < TOF_OFFSET ≤ REF_LPFM). If no line offset is required, then program TOF_OFFSET
equal to REF_LPFM instead of zero (invalid value).
Example:
If an input reference with PAL timing comes from the LMH1981, the H and V pulses will be aligned to within ΔT_HV
which occurs on line 313 of the reference. In this case, TOF_OFFSET can be set to 312d (138h) so the output
frame will align to Line 1 of the PAL reference (start of frame) after the outputs are initialized. This example is
illustrated in Figure 11.
PAL
500 mV/DIV
H sync
2.0V/DIV
V sync
2.0V/DIV
TOF
2.0V/DIV
TOF_OFFSET = 312
100 Ps/DIV
Figure 11. PAL Reference and Output TOF Pulse (TOF_OFFSET = 312)
NOTE
If the alternative set of divider and REF_LPFM values are programmed per ⁽¹⁾ for a lower
PLL 1 phase comparison frequency, then the output frame cannot be offset to any
horizontal line of the reference. Instead, the output frame can only be aligned to the
reference in 5 lines steps per 1 step of the TOF_OFFSET value, up to a maximum of
reference's total lines per frame divided by 5 (i.e. REF_LPFM). This is because the phase
comparison frequency (H_FB signal in Figure 9) will be lower than the H sync input
frequency by 5x due to the use of the alternative divider values.
Programming The Output Initialization Sequence
Before programming the output initialization (alignment) sequence, the following prerequisites must be met:
1. PLL 1 must be stable and locked to the input reference.
2. The desired output clock and TOF pulse timing must be fully specified to the output format registers.
(1) For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in
brackets “[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The
corresponding counter values for REF_LPFM needs to be programmed for proper reference frame and output timing generation. See
section Reference Frame Timing.
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