LMH1982SQ-NOPB Datasheet, PDF (12/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
SNLS289C – APRIL 2008 – REVISED MARCH 2013
www.ti.com
148.35 MHz PLL Initialization Sequence
The following programming sequence is required to initialize PLL 3 and generate a correct 148.35 MHz output
once it is selected as the HD_CLK; otherwise, the clock may have duty cycle errors, frequency errors, and/or
high jitter. This PLL initialization sequence must be programmed after switching from another HD clock frequency
or Hi-Z mode, as well as after a device reset or power cycle condition. Each programming step below represents
a separate write sequence.
1. Program HD_FREQ = 11b and HD_HIZ = 0 (register 08h) to select 148.35 MHz and enable the HD_CLK
output.
2. Program a value of 1 to the following register parameters (a single write sequence is valid for this step):
– FB_DIV = 1 (register 04h-05h)
– TOF_RST = 1 (register 09h-0Ah)
– REF_LPFM = 1 (register 0Fh-10h)
– EN_TOF_RST = 1 (register 0Ah)
3. Wait at least 2 cycles of the 27 MHz VCXO clock, then program EN_TOF_RST = 0.
After this sequence is completed, the 148.35 MHz clock will operate correctly and normal device configuration
can resume. All other output clocks do not require this initialization sequence for proper clock operation.
Enabling Genlock Mode
Upon device power up or reset, the default mode of operation is Free Run mode. To enable Genlock mode, set
GNLK = 1 (register 00h). Refer to section Genlock Mode.
Output Disturbance While Output Alignment Mode Enabled
When the output alignment mode is enabled (EN_TOF_RST = 1) for a longer period than is required by the
output initialization sequence, the output signals can be abruptly phase-aligned to the reference on every output
frame. Continual alignment can cause excessive phase “jumps” or jitter on the output clock edge coinciding with
the TOF pulse; this effect is unavoidable and can be caused by slight differences in the internal counter reset
timing for the TOF generation and also large input jitter. The characteristic of the output jitter can also vary in
severity from process variation, part variation, and the selected clock reference frequency. This output jitter can
only be inhibited by setting EN_TOF_RST = 0 immediately following the output initialization and before the
subsequent output frame.
Power Supply Sequencing
The V_DD (3.3V) and DV_DD (2.5V) power supply pins are isolated by internal ESD structures that may become
forward biased when DV_DD is higher than V_DD. Exposure to this condition, when prolonged and excessive, can
trigger latch-up and/or reduce the reliability of the device. Therefore, the LMH1982 has a recommended power
supply sequence.
On device power-up, the V_DD supply must be brought up before the DV_DD supply. On power-down, the DV_DD
supply must be brought down before the V_DD supply. The starting points and ramp rates of the supplies should
be considered to determine the relative timing of the power-up and power-down sequences such that DV_DD does
not exceed V_DD +0.3V as shown in the Absolute Maximum Ratings.
To minimize the potential for latch-up, a Schottky diode can be externally connected between the DV_DD supply
(anode) and V_DD supply (cathode). If DV_DD is brought up first, the Schottky will ensure that V_DD is within about
0.3V of DV_DD until V_DD is brought up.
Additionally, the device input pins (except for SDA and SCL inputs) should not be driven prior to power-up due to
the same reasons provided above for the power pins. Otherwise, a small series resistor should be used on each
input pin to protect the device by limiting the current whenever the internal ESD structures become forward
biased.
Once both supplies are powered up in the proper sequence, the device has a power on reset sequence that will
reset all registers to their default values.
12
Submit Documentation Feedback
Product Folder Links: LMH1982
Copyright © 2008–2013, Texas Instruments Incorporated