LMH1982SQ-NOPB Datasheet, PDF (19/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
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SNLS289C – APRIL 2008 – REVISED MARCH 2013
Output TOF Clock
The TOF pulse is derived from a counter chain, which receives either output clock (SD_CLK or HD_CLK) from a
2:1 MUX block, as shown in Figure 9. The TOF clock from the MUX can be selected by programming TOF_CLK
(register 0Ch). To select SD_CLK as the TOF clock, set TOF_CLK = 0; otherwise, set TOF_CLK = 1 to select
HD_CLK. The selected TOF clock frequency is determined by the SD_FREQ or HD_FREQ register setting.
The TOF output delay time (t_{D_TOF}) for any output format generated from a TOF clock of 27 MHz is specified in
Electrical Characteristics. The TOF output delay time for 525i and 1080i/50 generated using 27 MHz and 74.25
MHz, respectively, are shown in Typical Performance Characteristics. The TOF pulse width can be determined
by:
TOF pulse width = (1 / f_{TOF_CLK}) x TOF_PPL
where
•
f_{TOF_CLK} = Nominal TOF Clock Frequency
• TOF_PPL = Output Format Total Pixels per Line
(2)
Output Frame Timing
The TOF pulse is specified by programming TOF_CLK, TOF_PPL (register 0Bh-0Ch) and TOF_LPFM (register
0Dh-0Eh). These registers configure the 2:1 MUX and output pixel and line counters in the TOF Generation
blocks shown in Figure 9. The output frame or TOF pulse rate is determined by:
TOF rate = f_{TOF_CLK} / (TOF_PPL x TOF_LPFM)
where
•
f_{TOF_CLK} = Nominal TOF Clock Frequency
• TOF_PPL = Output Format Total Pixels per Line
• TOF_LPFM = Output Format Total Lines per Frame
(3)
Example:
If the output format is 625i, then:
TOF rate = 27 MHz / (1728 x 625) = 25 Hz
where
• f_{TOF_CLK} = 27 MHz (SD_FREQ = 0)
• TOF_PPL = 1728
• TOF_LPFM = 625
(4)
HD Format TOF Generation using a 27 MHz TOF Clock
Any HD format TOF pulse can be generated using either: Option 1) its native HD clock frequency, or Option 2)
the 27 MHz SD clock frequency.
Using for HD output formats can result in TOF output delay being offset by more than one TOF clock period,
even after output initialization. This is because the very short period of the HD native clock yields little timing
margin for the reset signals to propagate through the internal logic in Figure 9. For example, using a TOF clock
of 148.5 MHz gives less than 6.7 ns (< 1 clock cycle) for all the logic to completely synchronize and ensure
proper output initialization.
To ensure proper output initialization, is recommended for HD output formats, especially 1080p at 50, 59.94, and
60 Hz. This is because the longer period of the 27 MHz clock provides ample timing margin for the internal logic
to reset. The output parameters for programming the HD output formats using the 27 MHz clock are shown in
Table 1.
To illustrate both TOF clock options, an example is given below for 1080p/59.94, which has a native pixel clock
frequency of 148.5/1.001 MHz and frame rate of 60/1.001 Hz:
Option 1) 1080p/59.94 TOF generation using 148.35 MHz
TOF rate = 148.5/1.001 MHz / (2200 x 1125) = 60/1.001 Hz
where
•
•
f_{TOF_CLK} = 148.35 MHz (TOF_CLK = 1, HD_FREQ = 3h)
TOF_PPL = 2200
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