LMH1982SQ-NOPB Datasheet, PDF (11/43 Pages) Texas Instruments – Multi-Rate Video Clock Generator with Genlock

LMH1982
www.ti.com
SNLS289C – APRIL 2008 – REVISED MARCH 2013
APPLICATION INFORMATION
FUNCTIONAL OVERVIEW
The LMH1982 is an analog phase locked loop (PLL) clock generator that can output simultaneous SD and HD
video clocks synchronized or “genlocked” to H sync and V sync input reference timing. The LMH1982 features an
output Top of Frame (TOF) pulse generator with programmable timing that can also be synchronized to the
reference frame. Two reference ports are provided to allow a secondary input to be selected.
The clock generator uses a two-stage PLL architecture. The first stage is a VCXO-based PLL (PLL 1) that
requires an external 27 MHz VCXO and loop filter. In Genlock mode, PLL 1 can phase lock the VCXO clock to
the input reference after programming the PLL divider ratio. The use of a VCXO provides a low phase noise
clock source even when the LMH1982 is configured with a low loop bandwidth, which is necessary to attenuate
input timing jitter for minimum jitter transfer. The combination of the external VCXO, external loop filter, and
programmable PLL parameters can provide flexibility for the system designer to optimize the loop bandwidth and
loop response for the application.
The second stage consists of three PLLs (PLL 2, 3, 4) with integrated VCOs and loop filters. These PLLs will
attempt to continually track the reference VCXO clock phase from PLL 1 regardless of the device mode. The
second stage PLLs have pre-configured divider ratios to provide frequency multiplication or translation from the
VCXO clock frequency. The VCO PLLs use a high loop bandwidth to assure PLL stability, so the VCXO must
provide a stable low-jitter clock reference to ensure optimal output jitter performance.
Any unused clock output can be put in Hi-Z mode, which can be useful for reducing power dissipation as well as
reducing jitter or phase noise on the active clock output.
The TOF pulse can be programmed to indicate the start (top) of frame and even provide format cross-locking.
The output format registers should be programmed to specify the output timing (output clocks and TOF pulse),
the output timing offset relative to the reference, and the output initialization (alignment) to the reference frame. If
unused, the TOF output can also be put in Hi-Z mode.
When a loss of reference occurs during genlock, PLL 1 can default to either Free run or Holdover operation.
When free run is selected, the output frequency accuracy will be determined by the external bias on the free run
control voltage input pin, VC_FREERUN. When Holdover is selected, the loop filter can hold the control voltage
to maintain short-term output phase accuracy for a brief period in order to allow the application to select the
secondary input reference and re-lock the outputs. These options in combination with proper PLL 1 loop
response design can provide flexibility to manage output clock behavior during loss and re-acquisition of the
reference.
The reference status and PLL lock status flags can provide real-time status indication to the application system.
The loss of reference and lock detection thresholds can also be configured.
PLL
PLL 1
PLL 2
PLL 3
PLL 4
Input Reference
H sync
VCXO clock
VCXO clock
VCXO clock
Table 2. LMH1982 PLL and Clock Summary
Divider Ratio (reduced)
Programmable
11/4 or 11/2
250/91 or 500/91
5/2
Output Clock
Frequency (MHz)
27
74.25 or 148.5
74.25/1.001 (74.176) or 148.5/1.001
(148.35)
67.5
Output Port
SD_CLK
HD_CLK
HD_CLK
SD_CLK
GENERAL INFORMATION
For normal operation, the RESET pin must be set high; otherwise, the device cannot be programmed and will not
function properly. To reset the control registers to their default values, toggle RESET low for at least 10 µs and
then set high.
The LMH1982 can be configured by programming the control registers via the I²C interface. The I²C slave
addresses are DCh for write sequences and DDh for read sequences. The I²C_ENABLE pin must be set low or
tied to GND to allow I²C communication; otherwise, the LMH1982 will not acknowledge read/write sequences.
For I²C interface control register map and definitions, refer to section I²C INTERFACE CONTROL REGISTER
DEFINITIONS.
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