DS90UH927Q-Q1 Datasheet, PDF (9/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

www.ti.com
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.^(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
FPD-LINK LVDS INPUT
t_RSP
Receiver Strobe Position
See Figure 4
RxCLKIN±,
0.25
RXIN[3:0]±
FPD-LINK III CML I/O
t_LHT
CML Output Low-to-High Transition
Time
See Figure 3
t_HLT
CML Output High-to-Low Transition
Time
t_PLD
Serializer PLL Lock Time
See Figure 5, ⁽⁴⁾
DOUT+,
DOUT-
PCLK = 5 MHz
to 85 MHz
t_SD
Delay — Latency
See Figure 6
Checkerboard Pattern
Output Total Jitter,
PCLK=5 MHz, see Figure 8
t_TJIT
Bit Error Rate ≤1E-9, see Figure 7, ⁽⁵⁾
(6) (7) (8) (9)
Checkerboard Pattern
PCLK=85 MHz, see Figure 8
RxCLKIN±
f/40 < Jitter Freq < f/20, DES =
t_IJIT
Input Jitter Tolerance, Bit Error Rate
≤1E-9 ^{(8) (10)}
DS90UH926Q-Q1
f/40 < Jitter Freq < f/20, DES =
RxCLKIN±, f =
78 MHz
DS90UH928Q-Q1
I²S RECEIVER
T_I2S
I²S Clock Period, see Figure 10, ^{(7) (11)} RxCLKIN± f=5 MHz to 85 MHz
I2S_CLK,
PCLK = 5 MHz
to 85 MHz
T_HC
I²S Clock High Time, see Figure 10,
(11)
I2S_CLK
0.35
TYP
0.5
100
100
146*T
0.17
0.26
0.6
0.5
>4 /
PCLK or
>77
MAX UNIT
0.75 UI
140 ps
140 ps
5 ms
ns
0.2 UI
0.29 UI
UI
UI
ns
T_I2S
T_LC
I²S Clock Low Time, see Figure 10, ⁽¹¹⁾
t_sr
I²S Set-up Time
t_htr
I²S Hold Time
OTHER I/O
t_GPIO,FC
t_GPIO,BC
GPIO Pulse Width, Forward Channel
GPIO Pulse Width, Back Channel
I2S_CLK
0.35
T_I2S
I2S_WC
0.2
T_I2S
I2S_D[A,B,C,D]
I2S_WC
0.2
T_I2S
I2S_D[A,B,C,D]
GPIO[3:0],
PCLK = 5 MHz >2/PCLK
s
to 85 MHz
GPIO[3:0]
20
µs
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at V_DD33 = 3.3V, V_DDIO = 1.8V or 3.3V, T_A = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except V_OD and ΔV_OD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal
signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing
of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50
MHz.
(4) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.
(5) Output jitter specs are dependent upon the input clock jitter at the SER.
(6) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.
(7) Specification is ensured by design and is not tested in production.
(8) Specification is ensured by characterization and is not tested in production.
(9) t_TJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±.
(10) Jitter Frequency is specified in conjunction with DS90UH928Q-Q1 PLL bandwidth.
(11) I²S specifications for t_LC and t_HC pulses must each be greater than 2 PCLK periods to ensure sampling and supersedes the
0.35*T_{I2S_CLK} requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK.
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1
Submit Documentation Feedback
9