DS90UH927Q-Q1 Datasheet, PDF (18/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Feature Description (continued)
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Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 14. BIST Mode Flow Diagram
7.3.7 Forward Channel and Back Channel Error Checking
While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all
zeroes pattern. The internal all-zeroes pattern goes through scrambler, DC-balancing, and so forth, and is
transmitted over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the
recovered serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically
reported on the PASS pin of the deserializer.
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x0C[0] - Table 5). CRC errors are recorded in an 8-bit register in
the serializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer enters
BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode
CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or the
serializer enters BIST mode again.
BISTEN
(DES)
TxCLKOUT±
TxOUT[3:0]±
DATA
(internal)
PASS
Prior Result
DATA
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
X
BIST Test
BIST Duration
Figure 15. BIST Waveforms
PASS
FAIL
BIST
Result
Held
Normal
18
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