DS90UH927Q-Q1 Datasheet, PDF (48/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
Register Maps (continued)
ADD
(dec)
195
ADD
(hex)
0xC3
Table 5. Serial Control Bus Registers (continued)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
HDCP CTL
7
RW
0x00 HDCP RST HDCP Reset
Setting this bit will reset the HDCP transmitter and
disable HDCP authentication. This bit is self-clearing.
6
Reserved
5
RW
KSV List
Valid
The controller sets this bit after validating the
Repeater’s KSV List against the Key revocation list.
This allows completion of the Authentication process.
This bit is self-clearing.
4
RW
KSV Valid
The controller sets this bit after validating the
Receiver’s KSV against the Key revocation list. This
allows continuation of the Authentication process. This
bit will be cleared upon assertion of the KSV_RDY
flag in the HDCP_STS register. Setting this bit to a 0
will have no effect.
3
RW
HDCP ENC
DIS
HDCP Encrypt Disable
Disables HDCP encryption. Setting this bit to a 1 will
cause video data to be sent without encryption.
Authentication status will be maintained. This bit is
self-clearing.
2
RW
HDCP ENC
EN
HDCP Encrypt Enable
Enables HDCP encryption. When set, if the device is
authenticated, encrypted data will be sent. If device is
not authenticated, a blue screen will be sent.
Encryption should always be enabled when video
data requiring content protection is being supplied to
the transmitter. When this bit is not set, video data will
be sent without encryption. Note that when
CFG_ENC_MODE is set to Enc_Always, this bit will
be read only with a value of 1.
1
RW
HDCP DIS
HDCP Disable
Disables HDCP authentication. Setting this bit to a 1
will disable the HDCP authentication.
This bit is self-clearing.
0
RW
HDCP EN
HDCP Enable/Restart
Enables HDCP authentication. If HDCP is already
enabled, setting this bit to a 1 will restart
authentication. Setting this bit to a 0 will have no
effect. A register read will return the current HDCP
enabled status.
48
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1