DS90UH927Q-Q1 Datasheet, PDF (39/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Register Maps (continued)
ADD
(dec)
23
24
25
26
27
Table 5. Serial Control Bus Registers (continued)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0x17 I²C Control
7
RW
0x1E I²C Pass All Pass All
0: Enable Forward Control Channel pass-through only
of I²C accesses to I²C Slave IDs matching either the
remote Deserializer Slave ID or the remote Slave ID.
(default)
1: Enable Forward Control Channel pass-through of
all I²C accesses to I²C Slave IDs that do not match
the Serializer I²C Slave ID.
6:4
RW
SDA Hold
Time
Internal SDA Hold Time
Configures the amount of internal hold time provided
for the SDA input relative to the SCL input. Units are
40 nanoseconds.
3:0
RW
I²C Filter
Depth
Configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5
nanoseconds.
0x18 SCL High Time 7:0
RW
0xA1 SCL HIGH I²C Master SCL High Time
Time
This field configures the high pulse width of the SCL
output when the Serializer is the Master on the local
I²C bus. Units are 40 ns for the nominal oscillator
clock frequency.
0x19 SCL Low Time
7:0
RW
0xA5 SCL LOW I²C SCL Low Time
Time
This field configures the low pulse width of the SCL
output when the Serializer is the Master on the local
I²C bus. This value is also used as the SDA setup
time by the I²C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 40 ns for the nominal
oscillator clock frequency.
0x1A Data Path
Control 2
7
RW
0x00 Block I²S Block automatic I²S mode configuration
Auto Config (repeater only)
0: I²S mode (2-channel, 4-channel, or surround) is
detected from the in-band audio signaling
1: Disable automatic detection of I²S mode
6:1
0
RW
I²S
Surround
Reserved
Enable 5.1- or 7.1-channel I²S audio transport
0: 2-channel or 4-channel I²S audio is enabled as
configured in register 0x12 bits 3 and 0 (default)
1: 5.1- or 7.1-channel audio is enabled
Note that I²S Data Island Transport is the only option
for surround audio. Also note that in a repeater, this
bit may be overridden by the in-band I²S mode
detection.
0x1B BIST BC Error
7:0
R
0x00 BIST BC BIST Back Channel CRC Error Counter
Count
Errorr
This register stores the back-channel CRC error count
during BIST Mode (saturates at 255 errors). Clears
when a new BIST is initiated or by 0x04[5]
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