DS90UH927Q-Q1 Datasheet, PDF (16/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
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7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The High-Speed Forward Channel is composed of a 35-bit frame containing RGB data, sync signals, HDCP, I²C,
and I²S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the serial stream generated per
PCLK cycle into RxCLKIN±. This data payload is optimized for signal transmission over an AC coupled link. Data
is randomized, DC-balanced and scrambled.
C1
C0
Figure 13. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0).
This corresponds to an application payload rate range of 155 Mbps to 2.635 Gbps, with an actual line rate range
of 525 Mbps to 2.975 Gbps.
7.3.2 Low-Speed Back Channel Data Transfer
The Low-Speed Back Channel of the DS90UH927Q-Q1 provides bidirectional communication between the
display and host processor. Data is transferred simultaneously over the same physical link as the high-speed
forward channel data. The back channel transports I²C, HDCP, CRC, and 4 bits of standard GPIO information
with a 10 Mbps line rate.
7.3.3 Common Mode Filter Pin (CMF)
The serializer provides access to the center tap of the internal CML termination. A 0.1-μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 29). This
increases noise rejection capability in high-noise environments.
7.3.4 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the DS90UH927Q-Q1 applies a minimum pulse width
filter on these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 5. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 5. DE can have at most two transitions per 130 PCLKs.
7.3.5 EMI Reduction Features
7.3.5.1 LVCMOS V_DDIO Option
The 1.8-V or 3.3-V LVCMOS inputs and outputs are powered from separate VDDIO supply pins to offer
compatibility with external system interface signals. Note: When configuring the V_DDIO power supplies, all the
single-ended control input pins for device need to scale together with the same operating V_DDIO levels. If V_DDIO is
selected to operate in the 3.0 V to 3.6 V range, V_DDIO must be operated within 300 mV of V_DD33.
7.3.6 Built-In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-
speed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
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