DS90UH927Q-Q1 Datasheet, PDF (50/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
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Register Maps (continued)
ADD
(dec)
198
199
ADD
(hex)
0xC6
0xC7
Table 5. Serial Control Bus Registers (continued)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
HDCP ICR
7
RW
0x00 IE IND ACC Interrupt on Indirect Access Complete
Enables interrupt on completion of Indirect Register
Access.
6
RW
IE RXDET
INT
Interrupt on Receiver Detect
Enables interrupt on detection of a downstream
Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1,
the interrupt will wait for Receiver Lock Detect.
5
RW
IS_RX_INT
Interrupt on Receiver Interrupt
Enables interrupt on indication from the HDCP
Receiver. Allows propagation of interrupts from
downstream devices.
4
RW
IE LIST
RDY
Interrupt on KSV List Ready
Enables interrupt on KSV List Ready.
3
RW
IE KSV
RDY
Interrupt on KSV Ready
Enables interrupt on KSV Ready.
2
RW
IE AUTH
FAIL
Interrupt on Authentication Failure
Enables interrupt on authentication failure or loss of
authentication.
1
RW
IE AUTH
PASS
Interrupt on Authentication Pass
Enables interrupt on successful completion of
authentication.
0
RW
INT Enable Global Interrupt Enable
Enables interrupt on the interrupt signal to the
controller.
HDCP ISR
7
R
0x00 IS IND ACC Interrupt on Indirect Access Complete
Indirect Register Access has completed.
6
R
INT Detect Interrupt on Receiver Detect interrupt
A downstream receiver has been detected.
5
R
IS RX INT
Interrupt on Receiver interrupt
Receiver has indicated an interrupt request from
downstream device.
4
R
IS LIST
RDY
Interrupt on KSV List Ready
The KSV list is ready for reading by the controller.
3
R
IS KSV
RDY
Interrupt on KSV Ready
The Receiver KSV is ready for reading by the
controller.
2
R
IS AUTH
FAIL
Interrupt on Authentication Failure
Authentication failure or loss of authentication has
occurred.
1
R
IS AUTH
PASS
Interrupt on Authentication Pass
Authentication has completed successfully.
0
R
INT
Global Interrupt
Set if any enabled interrupt is indicated.
50
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