DS90UH927Q-Q1 Datasheet, PDF (25/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Device Functional Modes (continued)
7.4.3 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (Table 5) or LFMODE Pin. This mode optimizes device operation for lower input
data clock ranges supported by the serializer. If LFMODE is Low (LFMODE = 0, default), the RxCLKIN±
frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE = 1), the RxCLKIN± frequency is
between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB reset is required. When
LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by four. Thus, for the
operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective data payload of
175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative to the input
data rate remains the same.
7.4.4 FPD-Link Input Frame and Color Bit Mapping Select
The DS90UH927Q-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes:
LSBs on RxIN[3]±, shown in Figure 19, or MSBs on RxIN[3], shown in Figure 20. Each frame corresponds to a
single pixel clock (PCLK) cycle. The LVDS clock input to RxCLKIN± follows a 4:3 duty cycle scheme, with each
28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The
mapping scheme is controlled by MAPSEL pin or by Register (Table 5).
RxCLKIN +/-
RxIN3 +/-
RxIN2 +/-
RxIN1 +/-
RxIN0 +/-
Previous cycle
B[1]
(bit 26)
DE
(bit 20)
VS
(bit 19)
Current cycle (PCLK Period)
B[0]
(bit 25)
HS
(bit 18)
G[1]
(bit 24)
G[0]
(bit 23)
B[7]
(bit 17)
B[6]
(bit 16)
R[1]
(bit 22)
B[5]
(bit 15)
R[0]
(bit 21)
B[4]
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
Figure 19. FPD-Link Mapping: LSBs on RxIN3 (MAPSEL=L)
G[3]
(bit 7)
R[2]
(bit 0)
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