DS90UH927Q-Q1 Datasheet, PDF (54/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Typical Application (continued)
8.2.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 6. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for DOUT±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
85 MHz
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8.2.2 Detailed Design Procedure
Figure 29 shows a typical application of the DS90UH927Q-Q1 serializer for an 85-MHz 24-bit Color Display
Application. The CML outputs must have an external 0.1-μF AC coupling capacitor on the high speed serial lines.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7-μF capacitors and two (2)
additional 1-μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)
VDDs (VDD33 and VDDIO) for effective noise suppression. An RC delay is placed on the PDB signal to delay
the enabling of the device until power is stable.
8.2.3 Application Curves
Figure 31. Serializer Output Stream with 48-MHz Input
Clock
Figure 32. Serializer Eye with 48-MHz Input Clock
9 Power Supply Recommendations
The power supply ramp (V_DD33 and V_DDIO) should be faster than 1.5 ms with a monotonic rise. A large capacitor
on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended
operating voltage. When PDB pin is pulled up to V_DD33, a 10-kΩ pullup and a > 10-μF capacitor to GND are
required to delay the PDB input signal rise. All inputs must not be driven until both V_DD33 and V_DDIO has reached
steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed, and driven to the
same potential (they are not internally connected).
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