DS90UH927Q-Q1 Datasheet, PDF (21/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Feature Description (continued)
6. Disable I²C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0
7.3.10 Input RxCLKIN Loss Detect
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A
clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,
the serializer will then lock to the incoming RxCLKIN±. Note: when RxCLKIN± is lost, the optional Serial Bus
Control Registers values are still retained. See (Table 5) for more information.
7.3.11 Serial Link Fault Detect
The DS90UH927Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 5). The DS90UH927Q-Q1 will
detect any of the following conditions:
1. Cable open
2. + to - short
3. + to GND short
4. - to GND short
5. + to battery short
6. - to battery short
7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed)
NOTE
The device will detect any of the above conditions, but does not report specifically which
one has occurred.
7.3.12 INTERRUPT Pin (INTB)
1. On the DS90UH927Q-Q1 serializer, set register reg_0xC6[5] = 1 and 0xC6[0] = 1 (Table 5) to configure the
interrupt.
2. On the serializer, read from HDCP_ISR register 0xC7 to arm the interrupt for the first time.
3. When INTB_IN on the deserializer (DS90UH926Q-Q1 or DS90UH928Q-Q1) is set LOW, the INTB pin on the
serializer also pulls low, indicating an interrupt condition.
4. The external controller detects INTB = LOW and reads the HDCP_ISR register (Table 5) to determine the
interrupt source. Reading this register also clears and resets the interrupt.
7.3.13 General-Purpose I/O
7.3.13.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (inputs) or back
channel (outputs) applications. GPIO modes may be configured from the registers (Table 5). GPIO[1:0] are
dedicated pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UH927Q-Q1 is
paired with a DS90UH926Q-Q1 deserializer, the devices must be configured into 18-bit mode to allow usage of
GPIO pins on the DS90UH927 serializer. To enable 18-bit mode, set serializer register reg_0x12[2] = 1. 18-bit
mode will be auto-loaded into the deserializer from the serializer. See Table 1 for GPIO enable and configuration.
DESCRIPTION
GPIO3
GPIO2
Table 1. GPIO Enable and Configuration
DEVICE
DS90UH927Q-Q1
DS90UH926/8Q-Q1
DS90UH927Q-Q1
DS90UH926/8Q-Q1
FORWARD CHANNEL
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
BACK CHANNEL
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
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