DS90UH927Q-Q1 Datasheet, PDF (24/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
7.3.14.1 I²S Transport Modes
By default, audio is packetized and transmitted during video blanking periods in dedicated Data Island Transport
frames. Data Island frames may be disabled from control registers if Forward Channel Frame Transport of I²S
data is desired. In this mode, only I2S_DA is transmitted to the DS90UH928Q-Q1 deserializer. If connected to a
DS90UH926Q-Q1 deserializer, I2S_DA and I2S_DB are transmitted. Surround Sound Mode, which transmits all
four I²S data inputs (I2S_D[A..D]), may only be operated in Data Island Transport mode. This mode is only
available when connected to a DS90UH928Q-Q1 deserializer.
7.3.14.2 I²S Repeater
I²S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data
Island Transport on the FPD-Link interface during the video blanking periods. If frame transport is desired, then
the I²S pins should be connected from the deserializer to all serializers. Activating surround sound at the top-
level deserializer automatically configures downstream DS90UH927Q-Q1 serializers and DS90UH928Q-Q1
deserializers for surround sound transport utilizing Data Island Transport. If 4-channel operation utilizing I2S_DA
and I2S_DB only is desired, this mode must be explicitly set in each serializer and deserializer control register
throughout the repeater tree (Table 5).
A DS90UH927Q-Q1 serializer configured in repeater mode may also regenerate I²S audio from its I²S input pins
in lieu of Data Island frames. See the HDCP Repeater Connection Diagram (Figure 23) and the I²C Control
Registers (Table 5) for additional details.
7.3.15 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 5) and the Pattern Generator
Indirect Data (PGID reg_0x67 — Table 5). See Application Note AN-2198 Exploring the Internal Test Pattern
Generation Feature of 720p (SNLA132).
7.4 Device Functional Modes
7.4.1 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an
external device, or through V_DDIO, where V_DDIO = 3.0 V to 3.6 V or V_DD33. To save power, disable the link when
the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high. In the case where PDB is pulled up to V_DDIO = 3.0 V to 3.6 V or V_DD33 directly, a 10-kΩ
pullup resistor and a >10-µF capacitor to ground are required (See Figure 29).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum period of time. See AC Electrical Characteristics for more information.
7.4.2 Backward Compatible Mode
The DS90UH927Q-Q1 is also backward compatible to DS90UR906Q, DS90UR908Q FPD, and DS90UR916Q
FPD-Link II deserializers for PCLK frequencies ranging from 5 MHz to 65 MHz. It is also backward compatible
with the DS90UR910Q for PCLK frequencies ranging from 5 MHz to 75 MHz. The serializer transmits 28-bits of
data over a single serial FPD-Link II pair operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to
a line rate of 140 Mbps to 2.1 Gbps. The Backward Compatibility configuration can be selected through the
BKWD pin or programmed through the configuration register (Table 5). The bidirectional control channel, HDCP,
bidirectional GPIOs, I²S, and interrupt (INTB) are not active in this mode. However, local I²C access to the
serializer is still available. Note: PCLK frequency range in this mode is 15 MHz to 75 MHz for LFMODE=0 and 5
MHZ to <15 MHz for LFMODE=1.
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